From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFA55C54EED for ; Mon, 30 Jan 2023 13:26:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236337AbjA3N0U (ORCPT ); Mon, 30 Jan 2023 08:26:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229694AbjA3N0R (ORCPT ); Mon, 30 Jan 2023 08:26:17 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54B6034C34; Mon, 30 Jan 2023 05:26:16 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E3AD160FE3; Mon, 30 Jan 2023 13:26:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4D848C433D2; Mon, 30 Jan 2023 13:26:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1675085175; bh=gffRbQEVs3gaaDJBHxfh42gSvqRNHC73rnP3QyhAyWE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=aoO9ajTFTagD0kjKNo9/Gi/u1m1+vaaABIhpovlsU9JE/bbc34lOQ47/M63+zk94F lmR/jbJsz/XN1Tiiw+nTZhGgmQtuFQ0r2MsYBfve6ulHhQnSbYtCdR+4ytPhJ+lSC2 K5YuXRl6GPaQRJnoWqdbMqr0VtO7OxvCUbyEcJrk36nU++0ujoi0QQfyGBkLvpD229 yjQeuY4RZe6kCSXVWiRFoF1gP5fav9hCztnbEikmiMsDvdPGm9slN4dLmEnK0wunld 2OlsjfvOIEjxuZONbAI0ibDRIZ87p+tNhumpQKeI/C3IN3LV4B0SWbtVG0TSiEOwhv G6ufXOeVzd2fA== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pMUAm-005ptr-Vy; Mon, 30 Jan 2023 13:26:13 +0000 Date: Mon, 30 Jan 2023 13:26:12 +0000 Message-ID: <874js8duh7.wl-maz@kernel.org> From: Marc Zyngier To: "Lad, Prabhakar" Cc: Geert Uytterhoeven , Biju Das , Magnus Damm , Rob Herring , Krzysztof Kozlowski , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Prabhakar Mahadev Lad Subject: Re: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node In-Reply-To: References: <20230127174014.251539-1-prabhakar.mahadev-lad.rj@bp.renesas.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: prabhakar.csengg@gmail.com, geert@linux-m68k.org, biju.das.jz@bp.renesas.com, magnus.damm@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 30 Jan 2023 13:13:26 +0000, "Lad, Prabhakar" wrote: > > Hi Geert, > > On Mon, Jan 30, 2023 at 10:05 AM Geert Uytterhoeven > wrote: > > > > On Fri, Jan 27, 2023 at 10:48 PM Biju Das wrote: > > > > Subject: Re: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node > > > > On Fri, Jan 27, 2023 at 6:38 PM Biju Das wrote: > > > > > > Subject: [PATCH] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU > > > > > > node > > > > > > > > > > > > From: Lad Prabhakar > > > > > > > > > > > > Enable the performance monitor unit for the Cortex-A55 cores on the > > > > > > RZ/G2L > > > > > > (r9a07g044) SoC. > > > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > > > > > > > --- > > > > > > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++ > > > > > > 1 file changed, 5 insertions(+) > > > > > > > > > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > > > > > b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > > > > > index 80b2332798d9..ff9bdc03a3ed 100644 > > > > > > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > > > > > > @@ -161,6 +161,11 @@ opp-50000000 { > > > > > > }; > > > > > > }; > > > > > > > > > > > > + pmu_a55 { > > > > > > + compatible = "arm,cortex-a55-pmu"; > > > > > > + interrupts-extended = <&gic GIC_PPI 7 > > > > > > + IRQ_TYPE_LEVEL_HIGH>; > > > > > > > > > > Just a question, Is it tested? > > > > Yes this was tested with perf test > > > > > > > > > timer node[1] defines irq type as LOW, here it is high. > > > > You are right looking at the RZG2L_InterruptMapping_rev01.xlsx this should > > > > be LOW. (I followed the SPI IRQS where all the LEVEL interrupts are HIGH) > > > > > > > > > Also do we need to define (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW) as > > > > it has 2 cores?? > > > > > > > > > No this is not required for example here [0] where it has 6 cores. > > > > > > I may be wrong, That is the only example[1], where the A55 PMU per cpu interrupts and number of a55 cores in the DT > > > are not matching. > > > > > > [1] > > > https://elixir.bootlin.com/linux/latest/B/ident/arm%2Ccortex-a55-pmu > > > > Indeed, this looks like an omission, propagated through > > arch/arm64/boot/dts/renesas/r8a779[afg]0.dtsi. > > > > And doesn't this apply to all PPI interrupts, i.e. shouldn't the GIC > > in arch/arm64/boot/dts/renesas/r9a07g0{43u,44u,54}.dtsi specify the > > mask in their interrupts properties, too? > > > I was under the impression that the GIC_CPU_MASK_SIMPLE(x) was only > needed if the driver handled per-cpu stuff. > > Marc, what should be the correct usage? I'm reading the DT correctly, this system has a GICv3, which is quite natural for an A55-based system. For this configuration, no mask is required. The CPU mask stuff only applies to pre-GICv3. With GICv3+, you simply cannot express such a mask, as there is no practical limit to the number of CPUs. M. -- Without deviation from the norm, progress is not possible.