From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-renesas-soc-owner@kernel.org>
X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
	aws-us-west-2-korg-lkml-1.web.codeaurora.org
X-Spam-Level: 
X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,
	HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS
	autolearn=no autolearn_force=no version=3.4.0
Received: from mail.kernel.org (mail.kernel.org [198.145.29.99])
	by smtp.lore.kernel.org (Postfix) with ESMTP id 4D6BFC47082
	for <linux-renesas-soc@archiver.kernel.org>; Mon, 24 May 2021 00:57:52 +0000 (UTC)
Received: from vger.kernel.org (vger.kernel.org [23.128.96.18])
	by mail.kernel.org (Postfix) with ESMTP id 2341561166
	for <linux-renesas-soc@archiver.kernel.org>; Mon, 24 May 2021 00:57:52 +0000 (UTC)
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S232166AbhEXA7S (ORCPT
        <rfc822;linux-renesas-soc@archiver.kernel.org>);
        Sun, 23 May 2021 20:59:18 -0400
Received: from relmlor2.renesas.com ([210.160.252.172]:58538 "EHLO
        relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL)
        by vger.kernel.org with ESMTP id S232050AbhEXA7S (ORCPT
        <rfc822;linux-renesas-soc@vger.kernel.org>);
        Sun, 23 May 2021 20:59:18 -0400
Date:   24 May 2021 09:57:49 +0900
X-IronPort-AV: E=Sophos;i="5.82,319,1613401200"; 
   d="scan'208";a="82005021"
Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151])
  by relmlie6.idc.renesas.com with ESMTP; 24 May 2021 09:57:49 +0900
Received: from mercury.renesas.com (unknown [10.166.252.133])
        by relmlir5.idc.renesas.com (Postfix) with ESMTP id D1180400A8BF;
        Mon, 24 May 2021 09:57:49 +0900 (JST)
Message-ID: <874ketosmq.wl-kuninori.morimoto.gx@renesas.com>
From:   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Magnus <magnus.damm@gmail.com>,
        Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
        Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>,
        Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
        hoai.luu.ub@renesas.com,
        Takeshi Kihara <takeshi.kihara.df@renesas.com>,
        Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>,
        Khiem Nguyen <khiem.nguyen.xt@renesas.com>,
        Hien Dang <hien.dang.eb@renesas.com>
Subject: Re: [PATCH 1/3] clk: renesas: r8a77995: Add ZA2 clock
In-Reply-To: <87a6otc89m.wl-kuninori.morimoto.gx@renesas.com>
References: <87k0nyci2t.wl-kuninori.morimoto.gx@renesas.com>
        <87im3ici1u.wl-kuninori.morimoto.gx@renesas.com>
        <CAMuHMdX-JK7eta966wsLC-sGf7Z81196wmUVs3eGyVmAwi7FWw@mail.gmail.com>
        <87a6otc89m.wl-kuninori.morimoto.gx@renesas.com>
User-Agent: Wanderlust/2.15.9 Emacs/26.3 Mule/6.0
MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue")
Content-Type: text/plain; charset=US-ASCII
Precedence: bulk
List-ID: <linux-renesas-soc.vger.kernel.org>
X-Mailing-List: linux-renesas-soc@vger.kernel.org


Hi Geert

> > This does not match the Hardware User's Manual (Rev. 2.20):
> >   1. ZA2 is not a fixed clock, but can be controlled through the ZA2CKCR
> >      register.  Adding support for that requires writing a custom clock
> >      driver.
> >      Of course we can consider it a fixed clock initially, and make it
> >      configurable later, when time permits.
> >   2. The parent clock is either PLL0D3 or S0, with a configurable
> >      post-divider of 2 or 4, yielding 200, 250, 400, or 500[*] MHz.
> >      Using plain PLL0D24 would mean a post-divider of 8, yielding
> >      125 MHz, which is not documented as a supported value.
> > 
> > [*] Using the default would mean:
> > 
> >     DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 4, 1);

PLL0 * 1/3 = 1GHz.
And default ZA2 on D3 is 500MHz thus it will be below
but am I misunderstanding ?

	- DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 4, 1);
	+ DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1);

Thank you for your help !!

Best regards
---
Kuninori Morimoto