From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com ([192.55.52.115]:65499 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754170AbcJZIyN (ORCPT ); Wed, 26 Oct 2016 04:54:13 -0400 From: Jani Nikula To: Dhinakaran Pandiyan , intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, Dhinakaran Pandiyan , stable@vger.kernel.org Subject: Re: [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio In-Reply-To: <1477438863-20299-1-git-send-email-dhinakaran.pandiyan@intel.com> References: <87d1iooknr.fsf@intel.com> <1477438863-20299-1-git-send-email-dhinakaran.pandiyan@intel.com> Date: Wed, 26 Oct 2016 11:54:10 +0300 Message-ID: <874m3zmqx9.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org List-ID: On Wed, 26 Oct 2016, Dhinakaran Pandiyan wrote: > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > Having a lower cdclk triggers pipe underruns, which then lead to displays > continuously cycling off and on. This is essential for DP MST audio as the > link is trained at HBR2 and 4 lanes by default. > > v3: Combine BDW pixel rate adjustments into a function (Jani) > v2: Restrict fix to BDW > Retain the set cdclk across modesets (Ville) > Cc: stable@vger.kernel.org > Signed-off-by: Dhinakaran Pandiyan > Reviewed-by: Ville Syrjälä Reviewed-by: Jani Nikula We'll need this fix for Skylake too, don't we? Maybe Kabylake? Please send a follow-up patch for Skylake with the changes mentioned inline below. BR, Jani. > --- > drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a94f7d1..efe46b4 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -10260,6 +10260,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) > bxt_set_cdclk(to_i915(dev), req_cdclk); > } > > +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > + int pixel_rate) > +{ > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > + if (crtc_state->ips_enabled) if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > + > + /* BSpec says "Do not use DisplayPort with CDCLK less than > + * 432 MHz, audio enabled, port width x4, and link rate > + * HBR2 (5.4 GHz), or else there may be audio corruption or > + * screen corruption." > + */ > + if (intel_crtc_has_dp_encoder(crtc_state) && > + crtc_state->has_audio && > + crtc_state->port_clock >= 540000 && > + crtc_state->lane_count == 4) > + pixel_rate = max(432000, pixel_rate); > + > + return pixel_rate; > +} > + > /* compute the max rate for new configuration */ > static int ilk_max_pixel_rate(struct drm_atomic_state *state) > { > @@ -10285,9 +10306,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) > > pixel_rate = ilk_pipe_pixel_rate(crtc_state); > > - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > + if (IS_BROADWELL(dev_priv)) if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) > + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, > + pixel_rate); > > intel_state->min_pixclk[i] = pixel_rate; > } -- Jani Nikula, Intel Open Source Technology Center From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio Date: Wed, 26 Oct 2016 11:54:10 +0300 Message-ID: <874m3zmqx9.fsf@intel.com> References: <87d1iooknr.fsf@intel.com> <1477438863-20299-1-git-send-email-dhinakaran.pandiyan@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <1477438863-20299-1-git-send-email-dhinakaran.pandiyan@intel.com> Sender: stable-owner@vger.kernel.org To: intel-gfx@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, Dhinakaran Pandiyan , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Wed, 26 Oct 2016, Dhinakaran Pandiyan wrote: > According to BSpec, cdclk has to be not less than 432 MHz with DP audio > enabled, port width x4, and link rate HBR2 (5.4 GHz) > > Having a lower cdclk triggers pipe underruns, which then lead to displays > continuously cycling off and on. This is essential for DP MST audio as the > link is trained at HBR2 and 4 lanes by default. > > v3: Combine BDW pixel rate adjustments into a function (Jani) > v2: Restrict fix to BDW > Retain the set cdclk across modesets (Ville) > Cc: stable@vger.kernel.org > Signed-off-by: Dhinakaran Pandiyan > Reviewed-by: Ville Syrjälä Reviewed-by: Jani Nikula We'll need this fix for Skylake too, don't we? Maybe Kabylake? Please send a follow-up patch for Skylake with the changes mentioned inline below. BR, Jani. > --- > drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a94f7d1..efe46b4 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -10260,6 +10260,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) > bxt_set_cdclk(to_i915(dev), req_cdclk); > } > > +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > + int pixel_rate) > +{ > + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > + if (crtc_state->ips_enabled) if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > + > + /* BSpec says "Do not use DisplayPort with CDCLK less than > + * 432 MHz, audio enabled, port width x4, and link rate > + * HBR2 (5.4 GHz), or else there may be audio corruption or > + * screen corruption." > + */ > + if (intel_crtc_has_dp_encoder(crtc_state) && > + crtc_state->has_audio && > + crtc_state->port_clock >= 540000 && > + crtc_state->lane_count == 4) > + pixel_rate = max(432000, pixel_rate); > + > + return pixel_rate; > +} > + > /* compute the max rate for new configuration */ > static int ilk_max_pixel_rate(struct drm_atomic_state *state) > { > @@ -10285,9 +10306,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) > > pixel_rate = ilk_pipe_pixel_rate(crtc_state); > > - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) > - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > + if (IS_BROADWELL(dev_priv)) if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) > + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, > + pixel_rate); > > intel_state->min_pixclk[i] = pixel_rate; > } -- Jani Nikula, Intel Open Source Technology Center