From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A69A7C433EF for ; Wed, 20 Jul 2022 09:45:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232772AbiGTJpa (ORCPT ); Wed, 20 Jul 2022 05:45:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230405AbiGTJp2 (ORCPT ); Wed, 20 Jul 2022 05:45:28 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6421AEE3F for ; Wed, 20 Jul 2022 02:45:25 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 02AAAB81EB1 for ; Wed, 20 Jul 2022 09:45:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B7478C3411E; Wed, 20 Jul 2022 09:45:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1658310322; bh=aehb2vEzH/4KGB23P72fH2CEhv2w4wOGRXR9VC4eeK0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Ru2iataoS3WnwRehXdua9jcZvHJl0s8DaF0ubF2NhYN1ObmcZaFKaVfBGCbGDQ6sg HJ/FnXB43kJbrWv+EdBKlsPUi0zDlzTP3FcCSOr0N1Q/ppQf7agefnGOGqpv+CjUMT u+fO0qGny1ljnlBjA0G/wlDo+ETS91yLd5Thc9n4JYxxq7PehDnqCTyiJcm1+0Rbc5 MYId4iT8D4/hgKKMQRO+M9QpgRsP/cnUE58Rbm4waJLznqu1VwaTufAz4nmY4kVYNn oUOoxTkcXrGo9nl5mUkjI5O5c6AuXrmsGNqE1YD4LHUEvACvrRL3Ppul2icWTY0YeA z3Z+vvsn5CSBw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oE6Ge-008kEn-KB; Wed, 20 Jul 2022 10:45:20 +0100 Date: Wed, 20 Jul 2022 10:45:20 +0100 Message-ID: <875yjsyv67.wl-maz@kernel.org> From: Marc Zyngier To: Ricardo Koller Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com, alexandru.elisei@arm.com, eric.auger@redhat.com, oliver.upton@linux.dev, reijiw@google.com Subject: Re: [kvm-unit-tests PATCH 3/3] arm: pmu: Remove checks for !overflow in chained counters tests In-Reply-To: References: <20220718154910.3923412-1-ricarkol@google.com> <20220718154910.3923412-4-ricarkol@google.com> <87edyhz68i.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ricarkol@google.com, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com, alexandru.elisei@arm.com, eric.auger@redhat.com, oliver.upton@linux.dev, reijiw@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Wed, 20 Jul 2022 09:40:01 +0100, Ricardo Koller wrote: > > On Tue, Jul 19, 2022 at 12:34:05PM +0100, Marc Zyngier wrote: > > On Mon, 18 Jul 2022 16:49:10 +0100, > > Ricardo Koller wrote: > > > > > > A chained event overflowing on the low counter can set the overflow flag > > > in PMOVS. KVM does not set it, but real HW and the fast-model seem to. > > > Moreover, the AArch64.IncrementEventCounter() pseudocode in the ARM ARM > > > (DDI 0487H.a, J1.1.1 "aarch64/debug") also sets the PMOVS bit on > > > overflow. > > > > Isn't this indicative of a bug in the KVM emulation? To be honest, the > > pseudocode looks odd. It says: > > > > > > if old_value<64:ovflw> != new_value<64:ovflw> then > > PMOVSSET_EL0 = '1'; > > PMOVSCLR_EL0 = '1'; > > > > > > which I find remarkably ambiguous. Is this setting and clearing the > > overflow bit? Or setting it in the single register that backs the two > > accessors in whatever way it can? > > > > If it is the second interpretation that is correct, then KVM > > definitely needs fixing > > I think it's the second, as those two "= '1'" apply to the non-chained > counters case as well, which should definitely set the bit in PMOVSSET. > > > (though this looks pretty involved for > > anything that isn't a SWINC event). > > Ah, I see, there's a pretty convenient kvm_pmu_software_increment() for > SWINC, but a non-SWINC event is implemented as a single 64-bit perf > event. Indeed. Which means we need to de-optimise chained counters to being 32bit events, which is pretty annoying (for rapidly firing events, the interrupt rate is going to be significantly higher). I guess we should also investigate the support for FEAT_PMUv3p5 and native 64bit counters. Someone is bound to build it at some point. Thanks, M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6811AC433EF for ; Wed, 20 Jul 2022 09:45:28 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 090074CFD8; Wed, 20 Jul 2022 05:45:28 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@kernel.org Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JpZA49HvmYGH; Wed, 20 Jul 2022 05:45:26 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id DB7394CFD1; Wed, 20 Jul 2022 05:45:26 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 604E74CFCB for ; Wed, 20 Jul 2022 05:45:25 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4AagLv06Cdor for ; Wed, 20 Jul 2022 05:45:24 -0400 (EDT) Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 4AA284CE54 for ; Wed, 20 Jul 2022 05:45:24 -0400 (EDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 582A76126A; Wed, 20 Jul 2022 09:45:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B7478C3411E; Wed, 20 Jul 2022 09:45:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1658310322; bh=aehb2vEzH/4KGB23P72fH2CEhv2w4wOGRXR9VC4eeK0=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Ru2iataoS3WnwRehXdua9jcZvHJl0s8DaF0ubF2NhYN1ObmcZaFKaVfBGCbGDQ6sg HJ/FnXB43kJbrWv+EdBKlsPUi0zDlzTP3FcCSOr0N1Q/ppQf7agefnGOGqpv+CjUMT u+fO0qGny1ljnlBjA0G/wlDo+ETS91yLd5Thc9n4JYxxq7PehDnqCTyiJcm1+0Rbc5 MYId4iT8D4/hgKKMQRO+M9QpgRsP/cnUE58Rbm4waJLznqu1VwaTufAz4nmY4kVYNn oUOoxTkcXrGo9nl5mUkjI5O5c6AuXrmsGNqE1YD4LHUEvACvrRL3Ppul2icWTY0YeA z3Z+vvsn5CSBw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oE6Ge-008kEn-KB; Wed, 20 Jul 2022 10:45:20 +0100 Date: Wed, 20 Jul 2022 10:45:20 +0100 Message-ID: <875yjsyv67.wl-maz@kernel.org> From: Marc Zyngier To: Ricardo Koller Subject: Re: [kvm-unit-tests PATCH 3/3] arm: pmu: Remove checks for !overflow in chained counters tests In-Reply-To: References: <20220718154910.3923412-1-ricarkol@google.com> <20220718154910.3923412-4-ricarkol@google.com> <87edyhz68i.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ricarkol@google.com, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com, alexandru.elisei@arm.com, eric.auger@redhat.com, oliver.upton@linux.dev, reijiw@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: drjones@redhat.com, kvm@vger.kernel.org, oliver.upton@linux.dev, kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Wed, 20 Jul 2022 09:40:01 +0100, Ricardo Koller wrote: > > On Tue, Jul 19, 2022 at 12:34:05PM +0100, Marc Zyngier wrote: > > On Mon, 18 Jul 2022 16:49:10 +0100, > > Ricardo Koller wrote: > > > > > > A chained event overflowing on the low counter can set the overflow flag > > > in PMOVS. KVM does not set it, but real HW and the fast-model seem to. > > > Moreover, the AArch64.IncrementEventCounter() pseudocode in the ARM ARM > > > (DDI 0487H.a, J1.1.1 "aarch64/debug") also sets the PMOVS bit on > > > overflow. > > > > Isn't this indicative of a bug in the KVM emulation? To be honest, the > > pseudocode looks odd. It says: > > > > > > if old_value<64:ovflw> != new_value<64:ovflw> then > > PMOVSSET_EL0 = '1'; > > PMOVSCLR_EL0 = '1'; > > > > > > which I find remarkably ambiguous. Is this setting and clearing the > > overflow bit? Or setting it in the single register that backs the two > > accessors in whatever way it can? > > > > If it is the second interpretation that is correct, then KVM > > definitely needs fixing > > I think it's the second, as those two "= '1'" apply to the non-chained > counters case as well, which should definitely set the bit in PMOVSSET. > > > (though this looks pretty involved for > > anything that isn't a SWINC event). > > Ah, I see, there's a pretty convenient kvm_pmu_software_increment() for > SWINC, but a non-SWINC event is implemented as a single 64-bit perf > event. Indeed. Which means we need to de-optimise chained counters to being 32bit events, which is pretty annoying (for rapidly firing events, the interrupt rate is going to be significantly higher). I guess we should also investigate the support for FEAT_PMUv3p5 and native 64bit counters. Someone is bound to build it at some point. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm