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Mon, 3 Oct 2022 14:02:52 +0100 (BST) References: <20220930212622.108363-1-richard.henderson@linaro.org> <20220930212622.108363-16-richard.henderson@linaro.org> User-agent: mu4e 1.9.0; emacs 28.2.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: peter.maydell@linux.org, alex.bennee@linux.org, Philippe =?utf-8?Q?Mat?= =?utf-8?Q?hieu-Daud=C3=A9?= , qemu-devel@nongnu.org Subject: Re: [PATCH v6 15/18] include/hw/core: Create struct CPUJumpCache Date: Mon, 03 Oct 2022 13:57:19 +0100 In-reply-to: <20220930212622.108363-16-richard.henderson@linaro.org> Message-ID: <877d1hnjpf.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Wrap the bare TranslationBlock pointer into a structure. > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Richard Henderson > --- > accel/tcg/tb-hash.h | 1 + > accel/tcg/tb-jmp-cache.h | 24 ++++++++++++++++++++++++ > include/exec/cpu-common.h | 1 + > include/hw/core/cpu.h | 15 +-------------- > include/qemu/typedefs.h | 1 + > accel/tcg/cpu-exec.c | 10 +++++++--- > accel/tcg/cputlb.c | 9 +++++---- > accel/tcg/translate-all.c | 28 +++++++++++++++++++++++++--- > hw/core/cpu-common.c | 3 +-- > plugins/core.c | 2 +- > trace/control-target.c | 2 +- > 11 files changed, 68 insertions(+), 28 deletions(-) > create mode 100644 accel/tcg/tb-jmp-cache.h > > diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h > index 0a273d9605..83dc610e4c 100644 > --- a/accel/tcg/tb-hash.h > +++ b/accel/tcg/tb-hash.h > @@ -23,6 +23,7 @@ > #include "exec/cpu-defs.h" > #include "exec/exec-all.h" > #include "qemu/xxhash.h" > +#include "tb-jmp-cache.h" >=20=20 > #ifdef CONFIG_SOFTMMU >=20=20 > diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h > new file mode 100644 > index 0000000000..2d8fbb1bfe > --- /dev/null > +++ b/accel/tcg/tb-jmp-cache.h > @@ -0,0 +1,24 @@ > +/* > + * The per-CPU TranslationBlock jump cache. > + * > + * Copyright (c) 2003 Fabrice Bellard > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef ACCEL_TCG_TB_JMP_CACHE_H > +#define ACCEL_TCG_TB_JMP_CACHE_H > + > +#define TB_JMP_CACHE_BITS 12 > +#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) > + > +/* > + * Accessed in parallel; all accesses to 'tb' must be atomic. > + */ > +struct CPUJumpCache { > + struct { > + TranslationBlock *tb; > + } array[TB_JMP_CACHE_SIZE]; > +}; > + > +#endif /* ACCEL_TCG_TB_JMP_CACHE_H */ When I saw this I wondered if... > diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h > index d909429427..c493510ee9 100644 > --- a/include/exec/cpu-common.h > +++ b/include/exec/cpu-common.h > @@ -38,6 +38,7 @@ void cpu_list_unlock(void); > unsigned int cpu_list_generation_id_get(void); >=20=20 > void tcg_flush_softmmu_tlb(CPUState *cs); > +void tcg_flush_jmp_cache(CPUState *cs); this helper and .... > diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c > index 3a63113c41..63ecc15236 100644 > --- a/accel/tcg/translate-all.c > +++ b/accel/tcg/translate-all.c .. this one should be moved into accel/tcg/tb-jmp-cache.c so we can keep all the jmp cache stuff nicely contained (and cut down the grab bag of content to translate-all a bit)? >=20=20 > +/* > + * Called by generic code at e.g. cpu reset after cpu creation, > + * therefore we must be prepared to allocate the jump cache. > + */ > +void tcg_flush_jmp_cache(CPUState *cpu) > +{ > + CPUJumpCache *jc =3D cpu->tb_jmp_cache; > + > + if (likely(jc)) { > + for (int i =3D 0; i < TB_JMP_CACHE_SIZE; i++) { > + qatomic_set(&jc->array[i].tb, NULL); > + } > + } else { > + /* This should happen once during realize, and thus never race. = */ > + jc =3D g_new0(CPUJumpCache, 1); > + jc =3D qatomic_xchg(&cpu->tb_jmp_cache, jc); > + assert(jc =3D=3D NULL); > + } > +} > + Anyway: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e