[Intel-gfx] [PATCH 00/16] drm/i915: DP per-lane drive settings for icl+

[Intel-gfx] [PATCH 00/16] drm/i915: DP per-lane drive settings for icl+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All the generic link training code should be in check now.
Let's move on to actually programming the each TX lane with
its own individual settings.

Ville Syrjälä (16):
  drm/i915: Remove pointless extra namespace from dkl/snps buf trans
    structs
  drm/i915: Shrink {icl_mg,tgl_dkl}_phy_ddi_buf_trans
  drm/i915: Use standard form terminating condition for lane for loops
  drm/i915: Add all per-lane register definitions for icl combo phy
  drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff
  drm/i915: Extract icl_combo_phy_loadgen_select()
  drm/i915: Stop using group access when progrmming icl combo phy TX
  drm/i915: Query the vswing levels per-lane for icl combo phy
  drm/i915: Query the vswing levels per-lane for icl mg phy
  drm/i915: Query the vswing levels per-lane for tgl dkl phy
  drm/i915: Query the vswing levels per-lane for snps phy
  drm/i915: Enable per-lane drive settings for icl+
  drm/i915: Use intel_de_rmw() for tgl dkl phy programming
  drm/i915: Use intel_de_rmw() for icl mg phy programming
  drm/i915: Use intel_de_rmw() for icl combo phy programming
  drm/i915: Fix icl+ combo phy static lane power down setup

 drivers/gpu/drm/i915/display/icl_dsi.c        |  14 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    |  10 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 265 ++++++++----------
 .../drm/i915/display/intel_ddi_buf_trans.h    |  18 +-
 .../drm/i915/display/intel_dp_link_training.c |   5 +-
 drivers/gpu/drm/i915/display/intel_snps_phy.c |   8 +-
 drivers/gpu/drm/i915/i915_reg.h               |  11 +-
 7 files changed, 154 insertions(+), 177 deletions(-)

-- 
2.32.0

[Intel-gfx] [PATCH 01/16] drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The struct itself already has sufficient namespace. No need to
duplicate it in the members.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c           |  6 +++---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 12 ++++++------
 drivers/gpu/drm/i915/display/intel_snps_phy.c      |  6 +++---
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3f7bbeb3e3cd..d85d731e37fb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1285,9 +1285,9 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 	dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
 		      DKL_TX_DE_EMPAHSIS_COEFF_MASK |
 		      DKL_TX_VSWING_CONTROL_MASK);
-	dpcnt_val = DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.dkl_vswing_control);
-	dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.dkl_de_emphasis_control);
-	dpcnt_val |= DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.dkl_preshoot_control);
+	dpcnt_val = DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing);
+	dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis);
+	dpcnt_val |= DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
 
 	for (ln = 0; ln < 2; ln++) {
 		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index 6cdb8e9073c7..82fdc5ecd9de 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -40,15 +40,15 @@ struct icl_mg_phy_ddi_buf_trans {
 };
 
 struct tgl_dkl_phy_ddi_buf_trans {
-	u32 dkl_vswing_control;
-	u32 dkl_preshoot_control;
-	u32 dkl_de_emphasis_control;
+	u32 vswing;
+	u32 preshoot;
+	u32 de_emphasis;
 };
 
 struct dg2_snps_phy_buf_trans {
-	u8 snps_vswing;
-	u8 snps_pre_cursor;
-	u8 snps_post_cursor;
+	u8 vswing;
+	u8 pre_cursor;
+	u8 post_cursor;
 };
 
 union intel_ddi_buf_trans_entry {
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index b18f08c851dc..5e20f340730f 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -68,9 +68,9 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
 	for (ln = 0; ln < 4; ln++) {
 		u32 val = 0;
 
-		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.snps_vswing);
-		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.snps_pre_cursor);
-		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.snps_post_cursor);
+		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
+		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor);
+		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor);
 
 		intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val);
 	}
-- 
2.32.0

[Intel-gfx] [PATCH 02/16] drm/i915: Shrink {icl_mg, tgl_dkl}_phy_ddi_buf_trans

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

All the values we have in {icl_mg,tgl_dkl}_phy_ddi_buf_trans
fit into u8. Shrink the types accordingly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index 82fdc5ecd9de..2133984a572b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -34,15 +34,15 @@ struct icl_ddi_buf_trans {
 };
 
 struct icl_mg_phy_ddi_buf_trans {
-	u32 cri_txdeemph_override_11_6;
-	u32 cri_txdeemph_override_5_0;
-	u32 cri_txdeemph_override_17_12;
+	u8 cri_txdeemph_override_11_6;
+	u8 cri_txdeemph_override_5_0;
+	u8 cri_txdeemph_override_17_12;
 };
 
 struct tgl_dkl_phy_ddi_buf_trans {
-	u32 vswing;
-	u32 preshoot;
-	u32 de_emphasis;
+	u8 vswing;
+	u8 preshoot;
+	u8 de_emphasis;
 };
 
 struct dg2_snps_phy_buf_trans {
-- 
2.32.0

[Intel-gfx] [PATCH 03/16] drm/i915: Use standard form terminating condition for lane for loops

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use <4 instead of <=3 as the terminating condition for the
loops over the 4 lanes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d85d731e37fb..b0bd50383d57 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1067,7 +1067,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 
 	/* Program PORT_TX_DW4 */
 	/* We cannot write to GRP. It would overwrite individual loadgen. */
-	for (ln = 0; ln <= 3; ln++) {
+	for (ln = 0; ln < 4; ln++) {
 		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
 		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 			 CURSOR_COEFF_MASK);
@@ -1114,7 +1114,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
 	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
 	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
 	 */
-	for (ln = 0; ln <= 3; ln++) {
+	for (ln = 0; ln < 4; ln++) {
 		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
 		val &= ~LOADGEN_SELECT;
 
-- 
2.32.0

[Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add the FOO_LN() register macros for all the icl combo phy registers.
Also get rid of the semi-pointless FOO_LN0() variants and just use
the parametrized version.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c         | 14 +++++++-------
 drivers/gpu/drm/i915/display/intel_combo_phy.c |  8 ++++----
 drivers/gpu/drm/i915/display/intel_ddi.c       | 14 +++++++-------
 drivers/gpu/drm/i915/i915_reg.h                | 10 ++++------
 4 files changed, 22 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 9ee62707ec72..168c84a74d30 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -233,7 +233,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 		 * Program voltage swing and pre-emphasis level values as per
 		 * table in BSPEC under DDI buffer programing
 		 */
-		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
+		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 		tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 		tmp |= SCALING_MODE_SEL(0x2);
 		tmp |= TAP2_DISABLE | TAP3_DISABLE;
@@ -247,7 +247,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 		tmp |= RTERM_SELECT(0x6);
 		intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
 
-		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
+		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
 		tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 			 RCOMP_SCALAR_MASK);
 		tmp |= SWING_SEL_UPPER(0x2);
@@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 		tmp &= ~FRC_LATENCY_OPTIM_MASK;
 		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 		intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
-		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
+		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
 		tmp &= ~FRC_LATENCY_OPTIM_MASK;
 		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
@@ -470,7 +470,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 				       tmp);
 
 			tmp = intel_de_read(dev_priv,
-					    ICL_PORT_PCS_DW1_LN0(phy));
+					    ICL_PORT_PCS_DW1_LN(0, phy));
 			tmp &= ~LATENCY_OPTIM_MASK;
 			tmp |= LATENCY_OPTIM_VAL(0x1);
 			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
@@ -489,7 +489,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 
 	/* clear common keeper enable bit */
 	for_each_dsi_phy(phy, intel_dsi->phys) {
-		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
+		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
 		tmp &= ~COMMON_KEEPER_EN;
 		intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
 		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
@@ -510,7 +510,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 
 	/* Clear training enable to change swing values */
 	for_each_dsi_phy(phy, intel_dsi->phys) {
-		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
+		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 		tmp &= ~TX_TRAINING_EN;
 		intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
@@ -523,7 +523,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 
 	/* Set training enable to trigger update */
 	for_each_dsi_phy(phy, intel_dsi->phys) {
-		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
+		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 		tmp |= TX_TRAINING_EN;
 		intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index bacdf8a16bcb..634e8d449457 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -220,13 +220,13 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
 		return false;
 
 	if (DISPLAY_VER(dev_priv) >= 12) {
-		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy),
+		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy),
 				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
 				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
 				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
 				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
 
-		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN0(phy),
+		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
 				     DCC_MODE_SELECT_MASK,
 				     DCC_MODE_SELECT_CONTINUOSLY);
 	}
@@ -343,13 +343,13 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 
 skip_phy_misc:
 		if (DISPLAY_VER(dev_priv) >= 12) {
-			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
+			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy));
 			val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
 			val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
 			val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
 			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
 
-			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
+			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
 			val &= ~DCC_MODE_SELECT_MASK;
 			val |= DCC_MODE_SELECT_CONTINUOSLY;
 			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b0bd50383d57..0c9ed705af47 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1047,7 +1047,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	}
 
 	/* Set PORT_TX_DW5 */
-	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
+	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 	val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
 		  TAP2_DISABLE | TAP3_DISABLE);
 	val |= SCALING_MODE_SEL(0x2);
@@ -1056,7 +1056,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
 
 	/* Program PORT_TX_DW2 */
-	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
+	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
 	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 		 RCOMP_SCALAR_MASK);
 	val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
@@ -1078,7 +1078,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	}
 
 	/* Program PORT_TX_DW7 */
-	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
+	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(0, phy));
 	val &= ~N_SCALAR_MASK;
 	val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
 	intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
@@ -1100,7 +1100,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
 	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
 	 * else clear to 0b.
 	 */
-	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
+	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		val &= ~COMMON_KEEPER_EN;
 	else
@@ -1109,7 +1109,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
 
 	/* 2. Program loadgen select */
 	/*
-	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
+	 * Program PORT_TX_DW4 depending on Bit rate and used lanes
 	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
 	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
 	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
@@ -1131,7 +1131,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
 
 	/* 4. Clear training enable to change swing values */
-	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
+	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 	val &= ~TX_TRAINING_EN;
 	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
 
@@ -1139,7 +1139,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
 	icl_ddi_combo_vswing_program(encoder, crtc_state);
 
 	/* 6. Set training enable to trigger update */
-	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
+	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 	val |= TX_TRAINING_EN;
 	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..5e7a55e6ef50 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1968,7 +1968,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
 #define ICL_PORT_PCS_DW1_AUX(phy)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
 #define ICL_PORT_PCS_DW1_GRP(phy)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
-#define ICL_PORT_PCS_DW1_LN0(phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
+#define ICL_PORT_PCS_DW1_LN(ln, phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
 #define   DCC_MODE_SELECT_MASK		(0x3 << 20)
 #define   DCC_MODE_SELECT_CONTINUOSLY	(0x3 << 20)
 #define   COMMON_KEEPER_EN		(1 << 26)
@@ -1989,7 +1989,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 #define ICL_PORT_TX_DW2_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
 #define ICL_PORT_TX_DW2_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
-#define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
+#define ICL_PORT_TX_DW2_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
 #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
 #define   SWING_SEL_UPPER_MASK		(1 << 15)
 #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
@@ -2001,7 +2001,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 #define ICL_PORT_TX_DW4_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
 #define ICL_PORT_TX_DW4_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
-#define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
 #define ICL_PORT_TX_DW4_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
 #define   LOADGEN_SELECT		(1 << 31)
 #define   POST_CURSOR_1(x)		((x) << 12)
@@ -2013,7 +2012,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 #define ICL_PORT_TX_DW5_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
 #define ICL_PORT_TX_DW5_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
-#define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
+#define ICL_PORT_TX_DW5_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
 #define   TX_TRAINING_EN		(1 << 31)
 #define   TAP2_DISABLE			(1 << 30)
 #define   TAP3_DISABLE			(1 << 29)
@@ -2024,14 +2023,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 #define ICL_PORT_TX_DW7_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
 #define ICL_PORT_TX_DW7_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
-#define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
 #define ICL_PORT_TX_DW7_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
 #define   N_SCALAR(x)			((x) << 24)
 #define   N_SCALAR_MASK			(0x7F << 24)
 
 #define ICL_PORT_TX_DW8_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
 #define ICL_PORT_TX_DW8_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
-#define ICL_PORT_TX_DW8_LN0(phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))
+#define ICL_PORT_TX_DW8_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
 #define   ICL_PORT_TX_DW8_ODCC_CLK_SEL		REG_BIT(31)
 #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK	REG_GENMASK(30, 29)
 #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2	REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
-- 
2.32.0

[Intel-gfx] [PATCH 05/16] drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

DKL_TX_LOADGEN_SHARING_PMD_DISABLE doesn't even seem to exist,
also the spec says to skip all loadgen stuff.

The code was dead anyway since it wasn't actually writing the value
anywhere.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 --------
 drivers/gpu/drm/i915/i915_reg.h          | 1 -
 2 files changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0c9ed705af47..b8ec53d9e3b0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1309,14 +1309,6 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 		val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
 		val &= ~DKL_TX_DP20BITMODE;
 		intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
-
-		if ((intel_crtc_has_dp_encoder(crtc_state) &&
-		     crtc_state->port_clock == 162000) ||
-		    (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
-		     crtc_state->port_clock == 594000))
-			val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
-		else
-			val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e7a55e6ef50..8c8152de643f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11022,7 +11022,6 @@ enum skl_power_gate {
 						     _DKL_TX_DPCNTL1)
 
 #define _DKL_TX_DPCNTL2				0x2C8
-#define  DKL_TX_LOADGEN_SHARING_PMD_DISABLE            REG_BIT(12)
 #define  DKL_TX_DP20BITMODE				(1 << 2)
 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
 						     _DKL_PHY1_BASE, \
-- 
2.32.0

[Intel-gfx] [PATCH 06/16] drm/i915: Extract icl_combo_phy_loadgen_select()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the convoluted loadgen calculation into a small helper.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b8ec53d9e3b0..d06c76694a08 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1023,6 +1023,18 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
 	return DP_TRAIN_PRE_EMPH_LEVEL_3;
 }
 
+static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
+					int lane)
+{
+	if (crtc_state->port_clock > 600000)
+		return 0;
+
+	if (crtc_state->lane_count == 4)
+		return lane >= 1 ? LOADGEN_SELECT : 0;
+	else
+		return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
+}
+
 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 					 const struct intel_crtc_state *crtc_state)
 {
@@ -1089,11 +1101,8 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	int width, rate, ln;
 	u32 val;
-
-	width = crtc_state->lane_count;
-	rate = crtc_state->port_clock;
+	int ln;
 
 	/*
 	 * 1. If port type is eDP or DP,
@@ -1117,11 +1126,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
 	for (ln = 0; ln < 4; ln++) {
 		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
 		val &= ~LOADGEN_SELECT;
-
-		if ((rate <= 600000 && width == 4 && ln >= 1) ||
-		    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
-			val |= LOADGEN_SELECT;
-		}
+		val |= icl_combo_phy_loadgen_select(crtc_state, ln);
 		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
 	}
 
-- 
2.32.0

[Intel-gfx] [PATCH 07/16] drm/i915: Stop using group access when progrmming icl combo phy TX

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Program each TX lane individually so that we can start to use per-lane
drive settings.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++++++++++++++----------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d06c76694a08..aa789cabc55b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1068,14 +1068,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
 
 	/* Program PORT_TX_DW2 */
-	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
-	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
-		 RCOMP_SCALAR_MASK);
-	val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
-	val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel);
-	/* Program Rcomp scalar for every table entry */
-	val |= RCOMP_SCALAR(0x98);
-	intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
+	for (ln = 0; ln < 4; ln++) {
+		val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
+		val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
+			 RCOMP_SCALAR_MASK);
+		val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
+		val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel);
+		/* Program Rcomp scalar for every table entry */
+		val |= RCOMP_SCALAR(0x98);
+		intel_de_write(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), val);
+	}
 
 	/* Program PORT_TX_DW4 */
 	/* We cannot write to GRP. It would overwrite individual loadgen. */
@@ -1090,10 +1092,12 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	}
 
 	/* Program PORT_TX_DW7 */
-	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(0, phy));
-	val &= ~N_SCALAR_MASK;
-	val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
-	intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
+	for (ln = 0; ln < 4; ln++) {
+		val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
+		val &= ~N_SCALAR_MASK;
+		val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
+		intel_de_write(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), val);
+	}
 }
 
 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
-- 
2.32.0

[Intel-gfx] [PATCH 08/16] drm/i915: Query the vswing levels per-lane for icl combo phy

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Prepare for per-lane drive settings by querying the desired vswing
level per-lane.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index aa789cabc55b..4c400f0e7347 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1039,7 +1039,6 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 					 const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	int level = intel_ddi_level(encoder, crtc_state, 0);
 	const struct intel_ddi_buf_trans *trans;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	int n_entries, ln;
@@ -1069,6 +1068,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 
 	/* Program PORT_TX_DW2 */
 	for (ln = 0; ln < 4; ln++) {
+		int level = intel_ddi_level(encoder, crtc_state, ln);
+
 		val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
 		val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 			 RCOMP_SCALAR_MASK);
@@ -1082,6 +1083,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	/* Program PORT_TX_DW4 */
 	/* We cannot write to GRP. It would overwrite individual loadgen. */
 	for (ln = 0; ln < 4; ln++) {
+		int level = intel_ddi_level(encoder, crtc_state, ln);
+
 		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
 		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 			 CURSOR_COEFF_MASK);
@@ -1093,6 +1096,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 
 	/* Program PORT_TX_DW7 */
 	for (ln = 0; ln < 4; ln++) {
+		int level = intel_ddi_level(encoder, crtc_state, ln);
+
 		val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
 		val &= ~N_SCALAR_MASK;
 		val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
-- 
2.32.0

[Intel-gfx] [PATCH 09/16] drm/i915: Query the vswing levels per-lane for icl mg phy

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Prepare for per-lane drive settings by querying the desired vswing
level per-lane.

Note that the code only does two loops, with each one writing the
levels for two TX lanes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4c400f0e7347..1874a2ca8f3b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1163,7 +1163,6 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
-	int level = intel_ddi_level(encoder, crtc_state, 0);
 	const struct intel_ddi_buf_trans *trans;
 	int n_entries, ln;
 	u32 val;
@@ -1188,12 +1187,18 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 
 	/* Program MG_TX_SWINGCTRL with values from vswing table */
 	for (ln = 0; ln < 2; ln++) {
+		int level;
+
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
+
 		val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
 		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
 		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
 			trans->entries[level].mg.cri_txdeemph_override_17_12);
 		intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
 
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
+
 		val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
 		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
 		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
@@ -1203,6 +1208,10 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 
 	/* Program MG_TX_DRVCTRL with values from vswing table */
 	for (ln = 0; ln < 2; ln++) {
+		int level;
+
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
+
 		val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
 		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
 			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
@@ -1213,6 +1222,8 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 			CRI_TXDEEMPH_OVERRIDE_EN;
 		intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
 
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
+
 		val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
 		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
 			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
-- 
2.32.0

[Intel-gfx] [PATCH 10/16] drm/i915: Query the vswing levels per-lane for tgl dkl phy

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Prepare for per-lane drive settings by querying the desired vswing
level per-lane.

Note that the code only does two loops, with each one writing the
levels for two TX lanes. The register offsets also look a bit funny
because each time through the loop we write to the exact same
register offsets. The crucial bit is the HIP_INDEX_REG
write that steers the same mmio window into different places.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 33 ++++++++++++++----------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1874a2ca8f3b..85247744e9dd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1295,9 +1295,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
-	int level = intel_ddi_level(encoder, crtc_state, 0);
 	const struct intel_ddi_buf_trans *trans;
-	u32 val, dpcnt_mask, dpcnt_val;
 	int n_entries, ln;
 
 	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
@@ -1307,28 +1305,35 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 		return;
 
-	dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
-		      DKL_TX_DE_EMPAHSIS_COEFF_MASK |
-		      DKL_TX_VSWING_CONTROL_MASK);
-	dpcnt_val = DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing);
-	dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis);
-	dpcnt_val |= DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
-
 	for (ln = 0; ln < 2; ln++) {
+		int level;
+		u32 val;
+
 		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
 			       HIP_INDEX_VAL(tc_port, ln));
 
 		intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
 
-		/* All the registers are RMW */
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
+
 		val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
-		val &= ~dpcnt_mask;
-		val |= dpcnt_val;
+		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
+			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+			 DKL_TX_VSWING_CONTROL_MASK);
+		val |= DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
+			DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
+			DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
 		intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
 
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
+
 		val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
-		val &= ~dpcnt_mask;
-		val |= dpcnt_val;
+		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
+			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+			 DKL_TX_VSWING_CONTROL_MASK);
+		val |= DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
+			DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
+			DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
 		intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
 
 		val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
-- 
2.32.0

[Intel-gfx] [PATCH 11/16] drm/i915: Query the vswing levels per-lane for snps phy

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Prepare for per-lane drive settings by querying the desired vswing
level per-lane.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 5e20f340730f..c2251218a39e 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -58,7 +58,6 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct intel_ddi_buf_trans *trans;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	int level = intel_ddi_level(encoder, crtc_state, 0);
 	int n_entries, ln;
 
 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
@@ -66,6 +65,7 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
 		return;
 
 	for (ln = 0; ln < 4; ln++) {
+		int level = intel_ddi_level(encoder, crtc_state, ln);
 		u32 val = 0;
 
 		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
-- 
2.32.0

[Intel-gfx] [PATCH 12/16] drm/i915: Enable per-lane drive settings for icl+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that the link buf_trans, link training, and the
combo/mg/dkl/snps phy programming are all fixed up we can
allow per-lane DP drive settings on icl+. Make it so.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 1a943ae38a6b..279371237fe9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -301,7 +301,10 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
 				       enum drm_dp_phy dp_phy)
 {
-	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy);
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
+		DISPLAY_VER(i915) >= 11;
 }
 
 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
-- 
2.32.0

[Intel-gfx] [PATCH 13/16] drm/i915: Use intel_de_rmw() for tgl dkl phy programming

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Streamline the code by using intel_de_rmw().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
 1 file changed, 16 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 85247744e9dd..3c1b289df2c0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1307,7 +1307,6 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 
 	for (ln = 0; ln < 2; ln++) {
 		int level;
-		u32 val;
 
 		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
 			       HIP_INDEX_VAL(tc_port, ln));
@@ -1316,29 +1315,26 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-		val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
-		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
-			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
-			 DKL_TX_VSWING_CONTROL_MASK);
-		val |= DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
-			DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
-			DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
-		intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
+		intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port),
+			     DKL_TX_PRESHOOT_COEFF_MASK |
+			     DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+			     DKL_TX_VSWING_CONTROL_MASK,
+			     DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
+			     DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
+			     DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot));
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-		val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
-		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
-			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
-			 DKL_TX_VSWING_CONTROL_MASK);
-		val |= DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
-			DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
-			DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
-		intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
+		intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port),
+			     DKL_TX_PRESHOOT_COEFF_MASK |
+			     DKL_TX_DE_EMPAHSIS_COEFF_MASK |
+			     DKL_TX_VSWING_CONTROL_MASK,
+			     DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
+			     DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
+			     DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot));
 
-		val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
-		val &= ~DKL_TX_DP20BITMODE;
-		intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
+		intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
+			     DKL_TX_DP20BITMODE, 0);
 	}
 }
 
-- 
2.32.0

[Intel-gfx] [PATCH 14/16] drm/i915: Use intel_de_rmw() for icl mg phy programming

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Streamline the code by using intel_de_rmw().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 111 ++++++++---------------
 1 file changed, 39 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3c1b289df2c0..ce8c85701cff 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1165,7 +1165,6 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
 	const struct intel_ddi_buf_trans *trans;
 	int n_entries, ln;
-	u32 val;
 
 	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
 		return;
@@ -1174,15 +1173,11 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 		return;
 
-	/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
 	for (ln = 0; ln < 2; ln++) {
-		val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
-		val &= ~CRI_USE_FS32;
-		intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
-
-		val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
-		val &= ~CRI_USE_FS32;
-		intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
+		intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
+			     CRI_USE_FS32, 0);
+		intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
+			     CRI_USE_FS32, 0);
 	}
 
 	/* Program MG_TX_SWINGCTRL with values from vswing table */
@@ -1191,19 +1186,15 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-		val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
-		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
-		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
-			trans->entries[level].mg.cri_txdeemph_override_17_12);
-		intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
+		intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
+			     CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
+			     CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-		val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
-		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
-		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
-			trans->entries[level].mg.cri_txdeemph_override_17_12);
-		intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
+		intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
+			     CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
+			     CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
 	}
 
 	/* Program MG_TX_DRVCTRL with values from vswing table */
@@ -1212,27 +1203,21 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-		val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
-		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
-			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
-		val |= CRI_TXDEEMPH_OVERRIDE_5_0(
-			trans->entries[level].mg.cri_txdeemph_override_5_0) |
-			CRI_TXDEEMPH_OVERRIDE_11_6(
-				trans->entries[level].mg.cri_txdeemph_override_11_6) |
-			CRI_TXDEEMPH_OVERRIDE_EN;
-		intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
+		intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
+			     CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
+			     CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
+			     CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
+			     CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
+			     CRI_TXDEEMPH_OVERRIDE_EN);
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-		val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
-		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
-			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
-		val |= CRI_TXDEEMPH_OVERRIDE_5_0(
-			trans->entries[level].mg.cri_txdeemph_override_5_0) |
-			CRI_TXDEEMPH_OVERRIDE_11_6(
-				trans->entries[level].mg.cri_txdeemph_override_11_6) |
-			CRI_TXDEEMPH_OVERRIDE_EN;
-		intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
+		intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
+			     CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
+			     CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
+			     CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
+			     CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
+			     CRI_TXDEEMPH_OVERRIDE_EN);
 
 		/* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
 	}
@@ -1243,50 +1228,32 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 	 * values from table for which TX1 and TX2 enabled.
 	 */
 	for (ln = 0; ln < 2; ln++) {
-		val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
-		if (crtc_state->port_clock < 300000)
-			val |= CFG_LOW_RATE_LKREN_EN;
-		else
-			val &= ~CFG_LOW_RATE_LKREN_EN;
-		intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
+		intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
+			     CFG_LOW_RATE_LKREN_EN,
+			     crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
 	}
 
 	/* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
 	for (ln = 0; ln < 2; ln++) {
-		val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
-		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
-		if (crtc_state->port_clock <= 500000) {
-			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
-		} else {
-			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
-				CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
-		}
-		intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
+		intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
+			     CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
+			     CFG_AMI_CK_DIV_OVERRIDE_EN,
+			     crtc_state->port_clock > 500000 ?
+			     CFG_AMI_CK_DIV_OVERRIDE_EN | CFG_AMI_CK_DIV_OVERRIDE_VAL(1) : 0);
 
-		val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
-		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
-		if (crtc_state->port_clock <= 500000) {
-			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
-		} else {
-			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
-				CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
-		}
-		intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
+		intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
+			     CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
+			     CFG_AMI_CK_DIV_OVERRIDE_EN,
+			     crtc_state->port_clock > 500000 ?
+			     CFG_AMI_CK_DIV_OVERRIDE_EN | CFG_AMI_CK_DIV_OVERRIDE_VAL(1) : 0);
 	}
 
 	/* Program MG_TX_PISO_READLOAD with values from vswing table */
 	for (ln = 0; ln < 2; ln++) {
-		val = intel_de_read(dev_priv,
-				    MG_TX1_PISO_READLOAD(ln, tc_port));
-		val |= CRI_CALCINIT;
-		intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
-			       val);
-
-		val = intel_de_read(dev_priv,
-				    MG_TX2_PISO_READLOAD(ln, tc_port));
-		val |= CRI_CALCINIT;
-		intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
-			       val);
+		intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
+			     0, CRI_CALCINIT);
+		intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
+			     0, CRI_CALCINIT);
 	}
 }
 
-- 
2.32.0

[Intel-gfx] [PATCH 15/16] drm/i915: Use intel_de_rmw() for icl combo phy programming

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Streamline the code by using intel_de_rmw().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 44 ++++++++++--------------
 1 file changed, 18 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ce8c85701cff..c7c86b497ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1070,14 +1070,11 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	for (ln = 0; ln < 4; ln++) {
 		int level = intel_ddi_level(encoder, crtc_state, ln);
 
-		val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
-		val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
-			 RCOMP_SCALAR_MASK);
-		val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
-		val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel);
-		/* Program Rcomp scalar for every table entry */
-		val |= RCOMP_SCALAR(0x98);
-		intel_de_write(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), val);
+		intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
+			     SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
+			     SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
+			     SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
+			     RCOMP_SCALAR(0x98));
 	}
 
 	/* Program PORT_TX_DW4 */
@@ -1085,23 +1082,20 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	for (ln = 0; ln < 4; ln++) {
 		int level = intel_ddi_level(encoder, crtc_state, ln);
 
-		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
-		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
-			 CURSOR_COEFF_MASK);
-		val |= POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1);
-		val |= POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2);
-		val |= CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff);
-		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
+		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
+			     POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
+			     POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
+			     POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
+			     CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
 	}
 
 	/* Program PORT_TX_DW7 */
 	for (ln = 0; ln < 4; ln++) {
 		int level = intel_ddi_level(encoder, crtc_state, ln);
 
-		val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
-		val &= ~N_SCALAR_MASK;
-		val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
-		intel_de_write(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), val);
+		intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
+			     N_SCALAR_MASK,
+			     N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
 	}
 }
 
@@ -1133,16 +1127,14 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
 	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
 	 */
 	for (ln = 0; ln < 4; ln++) {
-		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
-		val &= ~LOADGEN_SELECT;
-		val |= icl_combo_phy_loadgen_select(crtc_state, ln);
-		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
+		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
+			     LOADGEN_SELECT,
+			     icl_combo_phy_loadgen_select(crtc_state, ln));
 	}
 
 	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
-	val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
-	val |= SUS_CLOCK_CONFIG;
-	intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
+	intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
+		     0, SUS_CLOCK_CONFIG);
 
 	/* 4. Clear training enable to change swing values */
 	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
-- 
2.32.0

[Intel-gfx] [PATCH 16/16] drm/i915: Fix icl+ combo phy static lane power down setup

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Our lane power down defines already include the necessary shift,
don't shit them a second time.

Fortunately we masked off the correct bits, so we accidentally
left all lanes powered up all the time.

Bits 8-11 where we end up writing our misdirected lane mask are
documented as MBZ, but looks like you can actually write there
so they're not read only bits. No idea what side effect the
bogus register write might have.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4151
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 634e8d449457..f628e0542933 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -301,7 +301,7 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
 
 	val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy));
 	val &= ~PWR_DOWN_LN_MASK;
-	val |= lane_mask << PWR_DOWN_LN_SHIFT;
+	val |= lane_mask;
 	intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
 }
 
-- 
2.32.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings for icl+

[Patchwork]

== Series Details ==

Series: drm/i915: DP per-lane drive settings for icl+
URL   : https://patchwork.freedesktop.org/series/95535/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
284e669a57b2 drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs
0f71d656b29b drm/i915: Shrink {icl_mg, tgl_dkl}_phy_ddi_buf_trans
04357f3b75ae drm/i915: Use standard form terminating condition for lane for loops
b82774efb2b1 drm/i915: Add all per-lane register definitions for icl combo phy
1d228306b7da drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff
47e546461be6 drm/i915: Extract icl_combo_phy_loadgen_select()
7af002c94e9e drm/i915: Stop using group access when progrmming icl combo phy TX
d97a7168e4e8 drm/i915: Query the vswing levels per-lane for icl combo phy
ef435d41c784 drm/i915: Query the vswing levels per-lane for icl mg phy
-:35: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1192:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 		                                              ^

-:35: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1192:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 		                                                 ^

-:43: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#43: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1200:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 		                                              ^

-:43: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#43: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1200:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 		                                                 ^

-:54: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#54: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1213:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 		                                              ^

-:54: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#54: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1213:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 		                                                 ^

-:63: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#63: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1225:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 		                                              ^

-:63: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#63: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1225:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 		                                                 ^

total: 0 errors, 0 warnings, 8 checks, 43 lines checked
bf9f565f3d25 drm/i915: Query the vswing levels per-lane for tgl dkl phy
-:55: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#55: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1317:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 		                                              ^

-:55: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#55: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1317:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 		                                                 ^

-:68: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#68: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1328:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 		                                              ^

-:68: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#68: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1328:
+		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 		                                                 ^

total: 0 errors, 0 warnings, 4 checks, 56 lines checked
ae736094e5c7 drm/i915: Query the vswing levels per-lane for snps phy
026b4eacb6c2 drm/i915: Enable per-lane drive settings for icl+
720aa864e834 drm/i915: Use intel_de_rmw() for tgl dkl phy programming
c09c9f245da1 drm/i915: Use intel_de_rmw() for icl mg phy programming
-:56: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#56: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1191:
+			     CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));

-:67: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#67: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1197:
+			     CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));

-:87: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#87: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1209:
+			     CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |

-:88: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#88: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1210:
+			     CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |

-:105: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1218:
+			     CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |

-:106: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#106: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1219:
+			     CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |

total: 0 errors, 6 warnings, 0 checks, 158 lines checked
b6b8bd4a06e4 drm/i915: Use intel_de_rmw() for icl combo phy programming
9c1b9c51ad06 drm/i915: Fix icl+ combo phy static lane power down setup

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DP per-lane drive settings for icl+

[Patchwork]

== Series Details ==

Series: drm/i915: DP per-lane drive settings for icl+
URL   : https://patchwork.freedesktop.org/series/95535/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: DP per-lane drive settings for icl+

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8409 bytes --]

== Series Details ==

Series: drm/i915: DP per-lane drive settings for icl+
URL   : https://patchwork.freedesktop.org/series/95535/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10691 -> Patchwork_21271
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/index.html

Known issues
------------

  Here are the changes found in Patchwork_21271 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-gfx:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][1] ([fdo#109271]) +5 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-kbl-soraka/igt@amdgpu/amd_basic@cs-gfx.html

  * igt@amdgpu/amd_basic@semaphore:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][2] ([fdo#109271]) +27 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-snb-2600:        NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  * igt@core_hotunplug@unbind-rebind:
    - fi-bdw-5557u:       NOTRUN -> [WARN][4] ([i915#3718])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_exec_suspend@basic-s0:
    - fi-skl-6700k2:      [PASS][5] -> [DMESG-WARN][6] ([i915#1602])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/fi-skl-6700k2/igt@gem_exec_suspend@basic-s0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-skl-6700k2/igt@gem_exec_suspend@basic-s0.html
    - fi-tgl-1115g4:      [PASS][7] -> [FAIL][8] ([i915#1888])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-kefka:       [PASS][9] -> [INCOMPLETE][10] ([i915#2940])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-bsw-kefka/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@late_gt_pm:
    - fi-bsw-nick:        NOTRUN -> [DMESG-FAIL][11] ([i915#2927] / [i915#3428])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-skl-guc:         NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-skl-guc/igt@kms_chamelium@dp-crc-fast.html
    - fi-bdw-5557u:       NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-skl-guc:         NOTRUN -> [SKIP][14] ([fdo#109271]) +28 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-skl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-skl-guc:         NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
    - fi-bsw-kefka:       NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#1436] / [i915#2722] / [i915#3428])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-bsw-kefka/igt@runner@aborted.html
    - fi-skl-6700k2:      NOTRUN -> [FAIL][17] ([i915#3363])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-skl-6700k2/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-soraka:      [DMESG-WARN][18] ([i915#1982] / [i915#262]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [INCOMPLETE][20] ([i915#2940]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [INCOMPLETE][22] ([i915#3921]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-guc:         [FAIL][24] -> [SKIP][25] ([fdo#109271])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Participating hosts (43 -> 37)
------------------------------

  Additional (1): fi-skl-guc 
  Missing    (7): fi-ilk-m540 bat-dg1-6 fi-hsw-4200u fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 bat-jsl-1 


Build changes
-------------

  * Linux: CI_DRM_10691 -> Patchwork_21271

  CI-20190529: 20190529
  CI_DRM_10691: eb389599ad96f44ed6fe1770c4dbaa2e88bfa5bc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6235: 65dd7d484d5d09de196def254afebf41dfde1052 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21271: 9c1b9c51ad06bfec529e9721c8819a17a8904f99 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9c1b9c51ad06 drm/i915: Fix icl+ combo phy static lane power down setup
b6b8bd4a06e4 drm/i915: Use intel_de_rmw() for icl combo phy programming
c09c9f245da1 drm/i915: Use intel_de_rmw() for icl mg phy programming
720aa864e834 drm/i915: Use intel_de_rmw() for tgl dkl phy programming
026b4eacb6c2 drm/i915: Enable per-lane drive settings for icl+
ae736094e5c7 drm/i915: Query the vswing levels per-lane for snps phy
bf9f565f3d25 drm/i915: Query the vswing levels per-lane for tgl dkl phy
ef435d41c784 drm/i915: Query the vswing levels per-lane for icl mg phy
d97a7168e4e8 drm/i915: Query the vswing levels per-lane for icl combo phy
7af002c94e9e drm/i915: Stop using group access when progrmming icl combo phy TX
47e546461be6 drm/i915: Extract icl_combo_phy_loadgen_select()
1d228306b7da drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff
b82774efb2b1 drm/i915: Add all per-lane register definitions for icl combo phy
04357f3b75ae drm/i915: Use standard form terminating condition for lane for loops
0f71d656b29b drm/i915: Shrink {icl_mg, tgl_dkl}_phy_ddi_buf_trans
284e669a57b2 drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/index.html

[-- Attachment #2: Type: text/html, Size: 10256 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: DP per-lane drive settings for icl+

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30268 bytes --]

== Series Details ==

Series: drm/i915: DP per-lane drive settings for icl+
URL   : https://patchwork.freedesktop.org/series/95535/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10691_full -> Patchwork_21271_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_21271_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21271_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_21271_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-tglb:         NOTRUN -> [SKIP][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [PASS][2] -> [FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-iclb8/igt@i915_pm_dc@dc9-dpms.html

  
Known issues
------------

  Here are the changes found in Patchwork_21271_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@chamelium:
    - shard-tglb:         NOTRUN -> [SKIP][4] ([fdo#111827])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@feature_discovery@chamelium.html

  * igt@gem_create@create-massive:
    - shard-apl:          NOTRUN -> [DMESG-WARN][5] ([i915#3002])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl7/igt@gem_create@create-massive.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [PASS][6] -> [TIMEOUT][7] ([i915#2369] / [i915#3063] / [i915#3648])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-tglb6/igt@gem_eio@unwedge-stress.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb7/igt@gem_eio@unwedge-stress.html
    - shard-iclb:         [PASS][8] -> [TIMEOUT][9] ([i915#2369] / [i915#2481] / [i915#3070])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-iclb2/igt@gem_eio@unwedge-stress.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-iclb5/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          NOTRUN -> [FAIL][10] ([i915#2846])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#2846])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-glk3/igt@gem_exec_fair@basic-deadline.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-glk4/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-skl:          NOTRUN -> [SKIP][13] ([fdo#109271]) +109 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl4/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-glk8/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][16] -> [FAIL][17] ([i915#2842])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][18] -> [FAIL][19] ([i915#2842])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][20] ([i915#2842])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-kbl:          [PASS][21] -> [FAIL][22] ([i915#2842]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#2190])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl6/igt@gem_huc_copy@huc-copy.html
    - shard-skl:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#2190])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl4/igt@gem_huc_copy@huc-copy.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-apl:          NOTRUN -> [WARN][25] ([i915#2658])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl1/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
    - shard-kbl:          NOTRUN -> [SKIP][26] ([fdo#109271]) +87 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl4/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html

  * igt@gem_sync@basic-many-each:
    - shard-snb:          NOTRUN -> [INCOMPLETE][27] ([i915#2055])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-snb7/igt@gem_sync@basic-many-each.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3323])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl6/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gen9_exec_parse@unaligned-access:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([i915#2856]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@gen9_exec_parse@unaligned-access.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          [PASS][30] -> [INCOMPLETE][31] ([i915#3921])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-snb7/igt@i915_selftest@live@hangcheck.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-snb5/igt@i915_selftest@live@hangcheck.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-skl:          [PASS][32] -> [INCOMPLETE][33] ([i915#198])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-skl4/igt@i915_suspend@fence-restore-untiled.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl4/igt@i915_suspend@fence-restore-untiled.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [PASS][34] -> [DMESG-WARN][35] ([i915#180]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-apl6/igt@i915_suspend@sysfs-reader.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl6/igt@i915_suspend@sysfs-reader.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([fdo#111614]) +1 similar issue
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb8/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-skl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3777]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3777])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3777]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][40] ([i915#3722]) +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][41] ([i915#3689]) +4 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3886]) +14 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-skl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3886]) +4 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl3/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3886]) +4 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl1/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium@dp-hpd-fast:
    - shard-snb:          NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-snb2/igt@kms_chamelium@dp-hpd-fast.html

  * igt@kms_chamelium@vga-hpd-for-each-pipe:
    - shard-kbl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +9 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl4/igt@kms_chamelium@vga-hpd-for-each-pipe.html

  * igt@kms_color_chamelium@pipe-a-ctm-limited-range:
    - shard-apl:          NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +23 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl3/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html

  * igt@kms_color_chamelium@pipe-b-ctm-0-5:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([fdo#109284] / [fdo#111827]) +6 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@kms_color_chamelium@pipe-b-ctm-0-5.html

  * igt@kms_color_chamelium@pipe-b-ctm-max:
    - shard-skl:          NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl4/igt@kms_color_chamelium@pipe-b-ctm-max.html

  * igt@kms_concurrent@pipe-d:
    - shard-tglb:         NOTRUN -> [FAIL][50] ([i915#1385])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@kms_concurrent@pipe-d.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          NOTRUN -> [TIMEOUT][51] ([i915#1319])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl3/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@legacy:
    - shard-tglb:         NOTRUN -> [SKIP][52] ([fdo#111828]) +1 similar issue
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb8/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@srm:
    - shard-kbl:          NOTRUN -> [TIMEOUT][53] ([i915#1319])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl4/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][54] ([i915#3319]) +1 similar issue
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-32x32-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([i915#3359]) +2 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-32x10-rapid-movement.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-skl:          [PASS][56] -> [INCOMPLETE][57] ([i915#146] / [i915#300])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          [PASS][58] -> [FAIL][59] ([i915#2346])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@2x-flip-vs-rmfb:
    - shard-tglb:         NOTRUN -> [SKIP][60] ([fdo#111825]) +21 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@kms_flip@2x-flip-vs-rmfb.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-skl:          NOTRUN -> [FAIL][61] ([i915#79])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt:
    - shard-snb:          NOTRUN -> [SKIP][62] ([fdo#109271]) +177 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][63] -> [DMESG-WARN][64] ([i915#180]) +2 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-tglb:         [PASS][65] -> [INCOMPLETE][66] ([i915#456])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-tglb2/igt@kms_frontbuffer_tracking@psr-suspend.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb7/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][67] -> [FAIL][68] ([i915#1188]) +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#533])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl1/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][71] -> [FAIL][72] ([fdo#108145] / [i915#265]) +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][73] ([i915#265])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-kbl:          NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265]) +2 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
    - shard-kbl:          NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658]) +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
    - shard-apl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) +4 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
    - shard-skl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658]) +2 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl4/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][79] -> [SKIP][80] ([fdo#109441]) +2 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-iclb5/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_psr@psr2_primary_render:
    - shard-tglb:         NOTRUN -> [FAIL][81] ([i915#132] / [i915#3467])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@kms_psr@psr2_primary_render.html

  * igt@kms_sysfs_edid_timing:
    - shard-apl:          NOTRUN -> [FAIL][82] ([IGT#2])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl1/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-apl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#533]) +2 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl3/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-apl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#2437])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl1/igt@kms_writeback@writeback-pixel-formats.html

  * igt@nouveau_crc@pipe-c-ctx-flip-detection:
    - shard-tglb:         NOTRUN -> [SKIP][85] ([i915#2530])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@nouveau_crc@pipe-c-ctx-flip-detection.html

  * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
    - shard-apl:          NOTRUN -> [SKIP][86] ([fdo#109271]) +311 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl8/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html

  * igt@prime_nv_pcopy@test3_3:
    - shard-tglb:         NOTRUN -> [SKIP][87] ([fdo#109291]) +2 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb3/igt@prime_nv_pcopy@test3_3.html

  * igt@prime_vgem@fence-read-hang:
    - shard-tglb:         NOTRUN -> [SKIP][88] ([fdo#109295])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb8/igt@prime_vgem@fence-read-hang.html

  * igt@sysfs_clients@pidname:
    - shard-kbl:          NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl6/igt@sysfs_clients@pidname.html

  * igt@sysfs_clients@sema-10:
    - shard-skl:          NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2994]) +1 similar issue
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl3/igt@sysfs_clients@sema-10.html

  * igt@sysfs_clients@sema-50:
    - shard-apl:          NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994]) +6 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl7/igt@sysfs_clients@sema-50.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [FAIL][92] ([i915#2410]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-tglb1/igt@gem_ctx_persistence@many-contexts.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [FAIL][94] ([i915#2842]) -> [PASS][95] +2 similar issues
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglb:         [FAIL][96] ([i915#2842]) -> [PASS][97] +1 similar issue
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb2/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_workarounds@suspend-resume:
    - shard-tglb:         [INCOMPLETE][98] ([i915#456]) -> [PASS][99] +1 similar issue
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-tglb7/igt@gem_workarounds@suspend-resume.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-tglb8/igt@gem_workarounds@suspend-resume.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][100] ([i915#72]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][102] ([i915#2122]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-glk7/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-glk5/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
    - shard-glk:          [FAIL][104] ([i915#79]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [DMESG-WARN][106] ([i915#180]) -> [PASS][107] +4 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1:
    - shard-skl:          [FAIL][108] ([i915#2122]) -> [PASS][109] +2 similar issues
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
    - shard-iclb:         [SKIP][110] ([i915#3701]) -> [PASS][111] +1 similar issue
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-iclb4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][112] ([fdo#109441]) -> [PASS][113] +1 similar issue
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-skl:          [INCOMPLETE][114] ([i915#198]) -> [PASS][115] +1 similar issue
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  
#### Warnings ####

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
    - shard-iclb:         [SKIP][116] ([i915#658]) -> [SKIP][117] ([i915#2920]) +2 similar issues
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-iclb3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
    - shard-iclb:         [SKIP][118] ([i915#2920]) -> [SKIP][119] ([i915#658]) +1 similar issue
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130]) ([fdo#109271] / [i915#1814] / [i915#3002] / [i915#3363])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-kbl7/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-kbl6/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-kbl7/igt@runner@aborted.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-kbl6/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-kbl2/igt@runner@aborted.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-kbl6/igt@runner@aborted.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl7/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl6/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl6/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl7/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-kbl2/igt@runner@aborted.html
    - shard-apl:          ([FAIL][131], [FAIL][132]) ([i915#180] / [i915#3002] / [i915#3363]) -> ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#1610] / [i915#180] / [i915#3002] / [i915#3363])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-apl2/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-apl8/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl2/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl6/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl7/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-apl3/igt@runner@aborted.html
    - shard-snb:          ([FAIL][137], [FAIL][138]) ([i915#3002]) -> ([FAIL][139], [FAIL][140]) ([i915#2426] / [i915#3002])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-snb7/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-snb7/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-snb7/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-snb6/igt@runner@aborted.html
    - shard-skl:          ([FAIL][141], [FAIL][142]) ([i915#3002] / [i915#3363]) -> ([FAIL][143], [FAIL][144], [FAIL][145]) ([i915#2029] / [i915#3002] / [i915#3363])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-skl6/igt@runner@aborted.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10691/shard-skl1/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl3/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl2/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/shard-skl9/igt@runner@aborted.html

  
  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21271/index.html

[-- Attachment #2: Type: text/html, Size: 34055 bytes --]

Re: [Intel-gfx] [PATCH 01/16] drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs

[Jani Nikula]

On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The struct itself already has sufficient namespace. No need to
> duplicate it in the members.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c           |  6 +++---
>  drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 12 ++++++------
>  drivers/gpu/drm/i915/display/intel_snps_phy.c      |  6 +++---
>  3 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3f7bbeb3e3cd..d85d731e37fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1285,9 +1285,9 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
>  	dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
>  		      DKL_TX_DE_EMPAHSIS_COEFF_MASK |
>  		      DKL_TX_VSWING_CONTROL_MASK);
> -	dpcnt_val = DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.dkl_vswing_control);
> -	dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.dkl_de_emphasis_control);
> -	dpcnt_val |= DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.dkl_preshoot_control);
> +	dpcnt_val = DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing);
> +	dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis);
> +	dpcnt_val |= DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
>  
>  	for (ln = 0; ln < 2; ln++) {
>  		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> index 6cdb8e9073c7..82fdc5ecd9de 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> @@ -40,15 +40,15 @@ struct icl_mg_phy_ddi_buf_trans {
>  };
>  
>  struct tgl_dkl_phy_ddi_buf_trans {
> -	u32 dkl_vswing_control;
> -	u32 dkl_preshoot_control;
> -	u32 dkl_de_emphasis_control;
> +	u32 vswing;
> +	u32 preshoot;
> +	u32 de_emphasis;
>  };
>  
>  struct dg2_snps_phy_buf_trans {
> -	u8 snps_vswing;
> -	u8 snps_pre_cursor;
> -	u8 snps_post_cursor;
> +	u8 vswing;
> +	u8 pre_cursor;
> +	u8 post_cursor;
>  };
>  
>  union intel_ddi_buf_trans_entry {
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index b18f08c851dc..5e20f340730f 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -68,9 +68,9 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
>  	for (ln = 0; ln < 4; ln++) {
>  		u32 val = 0;
>  
> -		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.snps_vswing);
> -		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.snps_pre_cursor);
> -		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.snps_post_cursor);
> +		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
> +		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor);
> +		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor);
>  
>  		intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val);
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 02/16] drm/i915: Shrink {icl_mg, tgl_dkl}_phy_ddi_buf_trans

[Jani Nikula]

On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All the values we have in {icl_mg,tgl_dkl}_phy_ddi_buf_trans
> fit into u8. Shrink the types accordingly.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> index 82fdc5ecd9de..2133984a572b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> @@ -34,15 +34,15 @@ struct icl_ddi_buf_trans {
>  };
>  
>  struct icl_mg_phy_ddi_buf_trans {
> -	u32 cri_txdeemph_override_11_6;
> -	u32 cri_txdeemph_override_5_0;
> -	u32 cri_txdeemph_override_17_12;
> +	u8 cri_txdeemph_override_11_6;
> +	u8 cri_txdeemph_override_5_0;
> +	u8 cri_txdeemph_override_17_12;
>  };
>  
>  struct tgl_dkl_phy_ddi_buf_trans {
> -	u32 vswing;
> -	u32 preshoot;
> -	u32 de_emphasis;
> +	u8 vswing;
> +	u8 preshoot;
> +	u8 de_emphasis;
>  };
>  
>  struct dg2_snps_phy_buf_trans {

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 03/16] drm/i915: Use standard form terminating condition for lane for loops

[Jani Nikula]

On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use <4 instead of <=3 as the terminating condition for the
> loops over the 4 lanes.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d85d731e37fb..b0bd50383d57 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1067,7 +1067,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  
>  	/* Program PORT_TX_DW4 */
>  	/* We cannot write to GRP. It would overwrite individual loadgen. */
> -	for (ln = 0; ln <= 3; ln++) {
> +	for (ln = 0; ln < 4; ln++) {
>  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
>  		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
>  			 CURSOR_COEFF_MASK);
> @@ -1114,7 +1114,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
>  	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
>  	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
>  	 */
> -	for (ln = 0; ln <= 3; ln++) {
> +	for (ln = 0; ln < 4; ln++) {
>  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
>  		val &= ~LOADGEN_SELECT;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy

[Jani Nikula]

On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add the FOO_LN() register macros for all the icl combo phy registers.
> Also get rid of the semi-pointless FOO_LN0() variants and just use
> the parametrized version.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Might argue the phy should be before lane, but that's another
conversation.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c         | 14 +++++++-------
>  drivers/gpu/drm/i915/display/intel_combo_phy.c |  8 ++++----
>  drivers/gpu/drm/i915/display/intel_ddi.c       | 14 +++++++-------
>  drivers/gpu/drm/i915/i915_reg.h                | 10 ++++------
>  4 files changed, 22 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 9ee62707ec72..168c84a74d30 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -233,7 +233,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>  		 * Program voltage swing and pre-emphasis level values as per
>  		 * table in BSPEC under DDI buffer programing
>  		 */
> -		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> +		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
>  		tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
>  		tmp |= SCALING_MODE_SEL(0x2);
>  		tmp |= TAP2_DISABLE | TAP3_DISABLE;
> @@ -247,7 +247,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
>  		tmp |= RTERM_SELECT(0x6);
>  		intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
>  
> -		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> +		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
>  		tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>  			 RCOMP_SCALAR_MASK);
>  		tmp |= SWING_SEL_UPPER(0x2);
> @@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>  		tmp &= ~FRC_LATENCY_OPTIM_MASK;
>  		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>  		intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
> -		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> +		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
>  		tmp &= ~FRC_LATENCY_OPTIM_MASK;
>  		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>  		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
> @@ -470,7 +470,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>  				       tmp);
>  
>  			tmp = intel_de_read(dev_priv,
> -					    ICL_PORT_PCS_DW1_LN0(phy));
> +					    ICL_PORT_PCS_DW1_LN(0, phy));
>  			tmp &= ~LATENCY_OPTIM_MASK;
>  			tmp |= LATENCY_OPTIM_VAL(0x1);
>  			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
> @@ -489,7 +489,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>  
>  	/* clear common keeper enable bit */
>  	for_each_dsi_phy(phy, intel_dsi->phys) {
> -		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
> +		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
>  		tmp &= ~COMMON_KEEPER_EN;
>  		intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
>  		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
> @@ -510,7 +510,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>  
>  	/* Clear training enable to change swing values */
>  	for_each_dsi_phy(phy, intel_dsi->phys) {
> -		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> +		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
>  		tmp &= ~TX_TRAINING_EN;
>  		intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
>  		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
> @@ -523,7 +523,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>  
>  	/* Set training enable to trigger update */
>  	for_each_dsi_phy(phy, intel_dsi->phys) {
> -		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> +		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
>  		tmp |= TX_TRAINING_EN;
>  		intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
>  		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index bacdf8a16bcb..634e8d449457 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -220,13 +220,13 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
>  		return false;
>  
>  	if (DISPLAY_VER(dev_priv) >= 12) {
> -		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy),
> +		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy),
>  				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
>  				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
>  				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
>  				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
>  
> -		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN0(phy),
> +		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
>  				     DCC_MODE_SELECT_MASK,
>  				     DCC_MODE_SELECT_CONTINUOSLY);
>  	}
> @@ -343,13 +343,13 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
>  
>  skip_phy_misc:
>  		if (DISPLAY_VER(dev_priv) >= 12) {
> -			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
> +			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy));
>  			val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
>  			val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
>  			val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
>  			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
>  
> -			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
> +			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
>  			val &= ~DCC_MODE_SELECT_MASK;
>  			val |= DCC_MODE_SELECT_CONTINUOSLY;
>  			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index b0bd50383d57..0c9ed705af47 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1047,7 +1047,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	}
>  
>  	/* Set PORT_TX_DW5 */
> -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> +	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
>  	val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
>  		  TAP2_DISABLE | TAP3_DISABLE);
>  	val |= SCALING_MODE_SEL(0x2);
> @@ -1056,7 +1056,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
>  
>  	/* Program PORT_TX_DW2 */
> -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> +	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
>  	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>  		 RCOMP_SCALAR_MASK);
>  	val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
> @@ -1078,7 +1078,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	}
>  
>  	/* Program PORT_TX_DW7 */
> -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
> +	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(0, phy));
>  	val &= ~N_SCALAR_MASK;
>  	val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
>  	intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
> @@ -1100,7 +1100,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
>  	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
>  	 * else clear to 0b.
>  	 */
> -	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
> +	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  		val &= ~COMMON_KEEPER_EN;
>  	else
> @@ -1109,7 +1109,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  	/* 2. Program loadgen select */
>  	/*
> -	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
> +	 * Program PORT_TX_DW4 depending on Bit rate and used lanes
>  	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
>  	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
>  	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
> @@ -1131,7 +1131,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
>  	intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
>  
>  	/* 4. Clear training enable to change swing values */
> -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> +	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
>  	val &= ~TX_TRAINING_EN;
>  	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
>  
> @@ -1139,7 +1139,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
>  	icl_ddi_combo_vswing_program(encoder, crtc_state);
>  
>  	/* 6. Set training enable to trigger update */
> -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> +	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
>  	val |= TX_TRAINING_EN;
>  	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c..5e7a55e6ef50 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1968,7 +1968,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
>  #define ICL_PORT_PCS_DW1_AUX(phy)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
>  #define ICL_PORT_PCS_DW1_GRP(phy)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
> -#define ICL_PORT_PCS_DW1_LN0(phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
> +#define ICL_PORT_PCS_DW1_LN(ln, phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
>  #define   DCC_MODE_SELECT_MASK		(0x3 << 20)
>  #define   DCC_MODE_SELECT_CONTINUOSLY	(0x3 << 20)
>  #define   COMMON_KEEPER_EN		(1 << 26)
> @@ -1989,7 +1989,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  
>  #define ICL_PORT_TX_DW2_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
>  #define ICL_PORT_TX_DW2_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
> -#define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
> +#define ICL_PORT_TX_DW2_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
>  #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
>  #define   SWING_SEL_UPPER_MASK		(1 << 15)
>  #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
> @@ -2001,7 +2001,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  
>  #define ICL_PORT_TX_DW4_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
>  #define ICL_PORT_TX_DW4_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
> -#define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
>  #define ICL_PORT_TX_DW4_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
>  #define   LOADGEN_SELECT		(1 << 31)
>  #define   POST_CURSOR_1(x)		((x) << 12)
> @@ -2013,7 +2012,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  
>  #define ICL_PORT_TX_DW5_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
>  #define ICL_PORT_TX_DW5_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
> -#define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
> +#define ICL_PORT_TX_DW5_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
>  #define   TX_TRAINING_EN		(1 << 31)
>  #define   TAP2_DISABLE			(1 << 30)
>  #define   TAP3_DISABLE			(1 << 29)
> @@ -2024,14 +2023,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  
>  #define ICL_PORT_TX_DW7_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
>  #define ICL_PORT_TX_DW7_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
> -#define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
>  #define ICL_PORT_TX_DW7_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
>  #define   N_SCALAR(x)			((x) << 24)
>  #define   N_SCALAR_MASK			(0x7F << 24)
>  
>  #define ICL_PORT_TX_DW8_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
>  #define ICL_PORT_TX_DW8_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
> -#define ICL_PORT_TX_DW8_LN0(phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))
> +#define ICL_PORT_TX_DW8_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
>  #define   ICL_PORT_TX_DW8_ODCC_CLK_SEL		REG_BIT(31)
>  #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK	REG_GENMASK(30, 29)
>  #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2	REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 05/16] drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff

[Jani Nikula]

On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> DKL_TX_LOADGEN_SHARING_PMD_DISABLE doesn't even seem to exist,
> also the spec says to skip all loadgen stuff.
>
> The code was dead anyway since it wasn't actually writing the value
> anywhere.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I admit not looking this up in spec, but this is dead code removal
anyway...

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 8 --------
>  drivers/gpu/drm/i915/i915_reg.h          | 1 -
>  2 files changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 0c9ed705af47..b8ec53d9e3b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1309,14 +1309,6 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
>  		val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
>  		val &= ~DKL_TX_DP20BITMODE;
>  		intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
> -
> -		if ((intel_crtc_has_dp_encoder(crtc_state) &&
> -		     crtc_state->port_clock == 162000) ||
> -		    (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> -		     crtc_state->port_clock == 594000))
> -			val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
> -		else
> -			val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5e7a55e6ef50..8c8152de643f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11022,7 +11022,6 @@ enum skl_power_gate {
>  						     _DKL_TX_DPCNTL1)
>  
>  #define _DKL_TX_DPCNTL2				0x2C8
> -#define  DKL_TX_LOADGEN_SHARING_PMD_DISABLE            REG_BIT(12)
>  #define  DKL_TX_DP20BITMODE				(1 << 2)
>  #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
>  						     _DKL_PHY1_BASE, \

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 06/16] drm/i915: Extract icl_combo_phy_loadgen_select()

[Jani Nikula]

On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the convoluted loadgen calculation into a small helper.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++++++++++++++---------
>  1 file changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index b8ec53d9e3b0..d06c76694a08 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1023,6 +1023,18 @@ static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
>  	return DP_TRAIN_PRE_EMPH_LEVEL_3;
>  }
>  
> +static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
> +					int lane)
> +{
> +	if (crtc_state->port_clock > 600000)
> +		return 0;
> +
> +	if (crtc_state->lane_count == 4)
> +		return lane >= 1 ? LOADGEN_SELECT : 0;
> +	else
> +		return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
> +}
> +
>  static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  					 const struct intel_crtc_state *crtc_state)
>  {
> @@ -1089,11 +1101,8 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -	int width, rate, ln;
>  	u32 val;
> -
> -	width = crtc_state->lane_count;
> -	rate = crtc_state->port_clock;
> +	int ln;
>  
>  	/*
>  	 * 1. If port type is eDP or DP,
> @@ -1117,11 +1126,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
>  	for (ln = 0; ln < 4; ln++) {
>  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
>  		val &= ~LOADGEN_SELECT;
> -
> -		if ((rate <= 600000 && width == 4 && ln >= 1) ||
> -		    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
> -			val |= LOADGEN_SELECT;
> -		}
> +		val |= icl_combo_phy_loadgen_select(crtc_state, ln);
>  		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy

[Ville Syrjälä]

On Fri, Oct 08, 2021 at 01:21:42PM +0300, Jani Nikula wrote:
> On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Add the FOO_LN() register macros for all the icl combo phy registers.
> > Also get rid of the semi-pointless FOO_LN0() variants and just use
> > the parametrized version.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Might argue the phy should be before lane, but that's another
> conversation.

Agreed. For some reason these were done in the _exact_ opposite order
to the similar defines for earlier platforms. I was really tempted to
cocci these into conformance but decided to leave that out for now.
The series was getting big enough as is.

> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Thanks.

> 
> > ---
> >  drivers/gpu/drm/i915/display/icl_dsi.c         | 14 +++++++-------
> >  drivers/gpu/drm/i915/display/intel_combo_phy.c |  8 ++++----
> >  drivers/gpu/drm/i915/display/intel_ddi.c       | 14 +++++++-------
> >  drivers/gpu/drm/i915/i915_reg.h                | 10 ++++------
> >  4 files changed, 22 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index 9ee62707ec72..168c84a74d30 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -233,7 +233,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> >  		 * Program voltage swing and pre-emphasis level values as per
> >  		 * table in BSPEC under DDI buffer programing
> >  		 */
> > -		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > +		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> >  		tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
> >  		tmp |= SCALING_MODE_SEL(0x2);
> >  		tmp |= TAP2_DISABLE | TAP3_DISABLE;
> > @@ -247,7 +247,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> >  		tmp |= RTERM_SELECT(0x6);
> >  		intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);
> >  
> > -		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> > +		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
> >  		tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> >  			 RCOMP_SCALAR_MASK);
> >  		tmp |= SWING_SEL_UPPER(0x2);
> > @@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
> >  		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> >  		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> >  		intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);
> > -		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> > +		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
> >  		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> >  		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> >  		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
> > @@ -470,7 +470,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
> >  				       tmp);
> >  
> >  			tmp = intel_de_read(dev_priv,
> > -					    ICL_PORT_PCS_DW1_LN0(phy));
> > +					    ICL_PORT_PCS_DW1_LN(0, phy));
> >  			tmp &= ~LATENCY_OPTIM_MASK;
> >  			tmp |= LATENCY_OPTIM_VAL(0x1);
> >  			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
> > @@ -489,7 +489,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
> >  
> >  	/* clear common keeper enable bit */
> >  	for_each_dsi_phy(phy, intel_dsi->phys) {
> > -		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
> > +		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
> >  		tmp &= ~COMMON_KEEPER_EN;
> >  		intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
> >  		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
> > @@ -510,7 +510,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
> >  
> >  	/* Clear training enable to change swing values */
> >  	for_each_dsi_phy(phy, intel_dsi->phys) {
> > -		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > +		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> >  		tmp &= ~TX_TRAINING_EN;
> >  		intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
> >  		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
> > @@ -523,7 +523,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
> >  
> >  	/* Set training enable to trigger update */
> >  	for_each_dsi_phy(phy, intel_dsi->phys) {
> > -		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > +		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> >  		tmp |= TX_TRAINING_EN;
> >  		intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
> >  		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
> > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > index bacdf8a16bcb..634e8d449457 100644
> > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> > @@ -220,13 +220,13 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
> >  		return false;
> >  
> >  	if (DISPLAY_VER(dev_priv) >= 12) {
> > -		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy),
> > +		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy),
> >  				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
> >  				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
> >  				     ICL_PORT_TX_DW8_ODCC_CLK_SEL |
> >  				     ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
> >  
> > -		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN0(phy),
> > +		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy),
> >  				     DCC_MODE_SELECT_MASK,
> >  				     DCC_MODE_SELECT_CONTINUOSLY);
> >  	}
> > @@ -343,13 +343,13 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
> >  
> >  skip_phy_misc:
> >  		if (DISPLAY_VER(dev_priv) >= 12) {
> > -			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
> > +			val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy));
> >  			val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
> >  			val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
> >  			val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
> >  			intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
> >  
> > -			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
> > +			val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
> >  			val &= ~DCC_MODE_SELECT_MASK;
> >  			val |= DCC_MODE_SELECT_CONTINUOSLY;
> >  			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index b0bd50383d57..0c9ed705af47 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1047,7 +1047,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> >  	}
> >  
> >  	/* Set PORT_TX_DW5 */
> > -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > +	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> >  	val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> >  		  TAP2_DISABLE | TAP3_DISABLE);
> >  	val |= SCALING_MODE_SEL(0x2);
> > @@ -1056,7 +1056,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> >  	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
> >  
> >  	/* Program PORT_TX_DW2 */
> > -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
> > +	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
> >  	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> >  		 RCOMP_SCALAR_MASK);
> >  	val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
> > @@ -1078,7 +1078,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> >  	}
> >  
> >  	/* Program PORT_TX_DW7 */
> > -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
> > +	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(0, phy));
> >  	val &= ~N_SCALAR_MASK;
> >  	val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
> >  	intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
> > @@ -1100,7 +1100,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
> >  	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
> >  	 * else clear to 0b.
> >  	 */
> > -	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
> > +	val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
> >  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> >  		val &= ~COMMON_KEEPER_EN;
> >  	else
> > @@ -1109,7 +1109,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
> >  
> >  	/* 2. Program loadgen select */
> >  	/*
> > -	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
> > +	 * Program PORT_TX_DW4 depending on Bit rate and used lanes
> >  	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
> >  	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
> >  	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
> > @@ -1131,7 +1131,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
> >  	intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
> >  
> >  	/* 4. Clear training enable to change swing values */
> > -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > +	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> >  	val &= ~TX_TRAINING_EN;
> >  	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
> >  
> > @@ -1139,7 +1139,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
> >  	icl_ddi_combo_vswing_program(encoder, crtc_state);
> >  
> >  	/* 6. Set training enable to trigger update */
> > -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
> > +	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> >  	val |= TX_TRAINING_EN;
> >  	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
> >  }
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index a897f4abea0c..5e7a55e6ef50 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1968,7 +1968,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
> >  #define ICL_PORT_PCS_DW1_AUX(phy)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
> >  #define ICL_PORT_PCS_DW1_GRP(phy)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
> > -#define ICL_PORT_PCS_DW1_LN0(phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
> > +#define ICL_PORT_PCS_DW1_LN(ln, phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy))
> >  #define   DCC_MODE_SELECT_MASK		(0x3 << 20)
> >  #define   DCC_MODE_SELECT_CONTINUOSLY	(0x3 << 20)
> >  #define   COMMON_KEEPER_EN		(1 << 26)
> > @@ -1989,7 +1989,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  
> >  #define ICL_PORT_TX_DW2_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
> >  #define ICL_PORT_TX_DW2_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
> > -#define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
> > +#define ICL_PORT_TX_DW2_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy))
> >  #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
> >  #define   SWING_SEL_UPPER_MASK		(1 << 15)
> >  #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
> > @@ -2001,7 +2001,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  
> >  #define ICL_PORT_TX_DW4_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
> >  #define ICL_PORT_TX_DW4_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
> > -#define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
> >  #define ICL_PORT_TX_DW4_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
> >  #define   LOADGEN_SELECT		(1 << 31)
> >  #define   POST_CURSOR_1(x)		((x) << 12)
> > @@ -2013,7 +2012,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  
> >  #define ICL_PORT_TX_DW5_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
> >  #define ICL_PORT_TX_DW5_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
> > -#define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
> > +#define ICL_PORT_TX_DW5_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy))
> >  #define   TX_TRAINING_EN		(1 << 31)
> >  #define   TAP2_DISABLE			(1 << 30)
> >  #define   TAP3_DISABLE			(1 << 29)
> > @@ -2024,14 +2023,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >  
> >  #define ICL_PORT_TX_DW7_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
> >  #define ICL_PORT_TX_DW7_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
> > -#define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
> >  #define ICL_PORT_TX_DW7_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
> >  #define   N_SCALAR(x)			((x) << 24)
> >  #define   N_SCALAR_MASK			(0x7F << 24)
> >  
> >  #define ICL_PORT_TX_DW8_AUX(phy)		_MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
> >  #define ICL_PORT_TX_DW8_GRP(phy)		_MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
> > -#define ICL_PORT_TX_DW8_LN0(phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))
> > +#define ICL_PORT_TX_DW8_LN(ln, phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy))
> >  #define   ICL_PORT_TX_DW8_ODCC_CLK_SEL		REG_BIT(31)
> >  #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK	REG_GENMASK(30, 29)
> >  #define   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2	REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 16/16] drm/i915: Fix icl+ combo phy static lane power down setup

[Imre Deak]

On Wed, Oct 06, 2021 at 11:49:37PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Our lane power down defines already include the necessary shift,
> don't shit them a second time.
> 
> Fortunately we masked off the correct bits, so we accidentally
> left all lanes powered up all the time.
> 
> Bits 8-11 where we end up writing our misdirected lane mask are
> documented as MBZ, but looks like you can actually write there
> so they're not read only bits. No idea what side effect the
> bogus register write might have.
> 
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4151
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_combo_phy.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 634e8d449457..f628e0542933 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -301,7 +301,7 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
>  
>  	val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy));
>  	val &= ~PWR_DOWN_LN_MASK;
> -	val |= lane_mask << PWR_DOWN_LN_SHIFT;
> +	val |= lane_mask;
>  	intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
>  }
>  
> -- 
> 2.32.0
> 

Re: [Intel-gfx] [PATCH 16/16] drm/i915: Fix icl+ combo phy static lane power down setup

[Jani Nikula]

On Wed, 06 Oct 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Our lane power down defines already include the necessary shift,
> don't shit them a second time.

*chuckle*

>
> Fortunately we masked off the correct bits, so we accidentally
> left all lanes powered up all the time.
>
> Bits 8-11 where we end up writing our misdirected lane mask are
> documented as MBZ, but looks like you can actually write there
> so they're not read only bits. No idea what side effect the
> bogus register write might have.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4151
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_combo_phy.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 634e8d449457..f628e0542933 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -301,7 +301,7 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
>  
>  	val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy));
>  	val &= ~PWR_DOWN_LN_MASK;
> -	val |= lane_mask << PWR_DOWN_LN_SHIFT;
> +	val |= lane_mask;
>  	intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 07/16] drm/i915: Stop using group access when progrmming icl combo phy TX

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Program each TX lane individually so that we can start to use per-lane
> drive settings.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++++++++++++++----------
>  1 file changed, 16 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d06c76694a08..aa789cabc55b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1068,14 +1068,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
>  
>  	/* Program PORT_TX_DW2 */
> -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
> -	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> -		 RCOMP_SCALAR_MASK);
> -	val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
> -	val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel);
> -	/* Program Rcomp scalar for every table entry */
> -	val |= RCOMP_SCALAR(0x98);
> -	intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
> +	for (ln = 0; ln < 4; ln++) {
> +		val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
> +		val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> +			 RCOMP_SCALAR_MASK);
> +		val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
> +		val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel);
> +		/* Program Rcomp scalar for every table entry */
> +		val |= RCOMP_SCALAR(0x98);
> +		intel_de_write(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), val);
> +	}
>  
>  	/* Program PORT_TX_DW4 */
>  	/* We cannot write to GRP. It would overwrite individual loadgen. */
> @@ -1090,10 +1092,12 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	}
>  
>  	/* Program PORT_TX_DW7 */
> -	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(0, phy));
> -	val &= ~N_SCALAR_MASK;
> -	val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
> -	intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
> +	for (ln = 0; ln < 4; ln++) {
> +		val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
> +		val &= ~N_SCALAR_MASK;
> +		val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
> +		intel_de_write(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), val);
> +	}
>  }

Missing DSI conversion but from what I understood this conversion from group to lane is to support DP 2.0 so we can keep the group write for DSI.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

>  
>  static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,

Re: [Intel-gfx] [PATCH 08/16] drm/i915: Query the vswing levels per-lane for icl combo phy

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Prepare for per-lane drive settings by querying the desired vswing
> level per-lane.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index aa789cabc55b..4c400f0e7347 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1039,7 +1039,6 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  					 const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	int level = intel_ddi_level(encoder, crtc_state, 0);
>  	const struct intel_ddi_buf_trans *trans;
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  	int n_entries, ln;
> @@ -1069,6 +1068,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  
>  	/* Program PORT_TX_DW2 */
>  	for (ln = 0; ln < 4; ln++) {
> +		int level = intel_ddi_level(encoder, crtc_state, ln);
> +
>  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
>  		val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>  			 RCOMP_SCALAR_MASK);
> @@ -1082,6 +1083,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	/* Program PORT_TX_DW4 */
>  	/* We cannot write to GRP. It would overwrite individual loadgen. */
>  	for (ln = 0; ln < 4; ln++) {
> +		int level = intel_ddi_level(encoder, crtc_state, ln);
> +
>  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
>  		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
>  			 CURSOR_COEFF_MASK);
> @@ -1093,6 +1096,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  
>  	/* Program PORT_TX_DW7 */
>  	for (ln = 0; ln < 4; ln++) {
> +		int level = intel_ddi_level(encoder, crtc_state, ln);
> +
>  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
>  		val &= ~N_SCALAR_MASK;
>  		val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);

The cover letter or one of the earlier patches should have some explanation about the reasons of this the group to lane conversion.
Reading one of the later patches I understood is because DP 2.0 allows different level per lane but would be nice to know for sure the reason.

What if it is only using 2 lanes? Programming disabled lanes will cause any issue?

Re: [Intel-gfx] [PATCH 09/16] drm/i915: Query the vswing levels per-lane for icl mg phy

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Prepare for per-lane drive settings by querying the desired vswing
> level per-lane.
> 
> Note that the code only does two loops, with each one writing the
> levels for two TX lanes.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4c400f0e7347..1874a2ca8f3b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1163,7 +1163,6 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
> -	int level = intel_ddi_level(encoder, crtc_state, 0);
>  	const struct intel_ddi_buf_trans *trans;
>  	int n_entries, ln;
>  	u32 val;
> @@ -1188,12 +1187,18 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  	/* Program MG_TX_SWINGCTRL with values from vswing table */
>  	for (ln = 0; ln < 2; ln++) {
> +		int level;
> +
> +		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
> +
>  		val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
>  		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
>  		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
>  			trans->entries[level].mg.cri_txdeemph_override_17_12);
>  		intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
>  
> +		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
> +
>  		val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
>  		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
>  		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> @@ -1203,6 +1208,10 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  	/* Program MG_TX_DRVCTRL with values from vswing table */
>  	for (ln = 0; ln < 2; ln++) {
> +		int level;
> +
> +		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
> +
>  		val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
>  		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
>  			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> @@ -1213,6 +1222,8 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  			CRI_TXDEEMPH_OVERRIDE_EN;
>  		intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
>  
> +		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);

I believe our code style requires that we have spaces, so it should be (2 * ln + 1).

With the answers requested in the previous patch:

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


> +
>  		val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
>  		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
>  			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);

Re: [Intel-gfx] [PATCH 10/16] drm/i915: Query the vswing levels per-lane for tgl dkl phy

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Prepare for per-lane drive settings by querying the desired vswing
> level per-lane.
> 
> Note that the code only does two loops, with each one writing the
> levels for two TX lanes. The register offsets also look a bit funny
> because each time through the loop we write to the exact same
> register offsets. The crucial bit is the HIP_INDEX_REG
> write that steers the same mmio window into different places.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 33 ++++++++++++++----------
>  1 file changed, 19 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1874a2ca8f3b..85247744e9dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1295,9 +1295,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
> -	int level = intel_ddi_level(encoder, crtc_state, 0);
>  	const struct intel_ddi_buf_trans *trans;
> -	u32 val, dpcnt_mask, dpcnt_val;
>  	int n_entries, ln;
>  
>  	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
> @@ -1307,28 +1305,35 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
>  	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
>  		return;
>  
> -	dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
> -		      DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> -		      DKL_TX_VSWING_CONTROL_MASK);
> -	dpcnt_val = DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing);
> -	dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis);
> -	dpcnt_val |= DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
> -
>  	for (ln = 0; ln < 2; ln++) {
> +		int level;
> +		u32 val;
> +
>  		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
>  			       HIP_INDEX_VAL(tc_port, ln));
>  
>  		intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
>  
> -		/* All the registers are RMW */
> +		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
> +
>  		val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
> -		val &= ~dpcnt_mask;
> -		val |= dpcnt_val;
> +		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
> +			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> +			 DKL_TX_VSWING_CONTROL_MASK);
> +		val |= DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
> +			DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
> +			DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
>  		intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
>  
> +		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
> +
>  		val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
> -		val &= ~dpcnt_mask;
> -		val |= dpcnt_val;
> +		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
> +			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> +			 DKL_TX_VSWING_CONTROL_MASK);
> +		val |= DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
> +			DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
> +			DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
>  		intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
>  
>  		val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));

Re: [Intel-gfx] [PATCH 11/16] drm/i915: Query the vswing levels per-lane for snps phy

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Prepare for per-lane drive settings by querying the desired vswing
> level per-lane.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 5e20f340730f..c2251218a39e 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -58,7 +58,6 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	const struct intel_ddi_buf_trans *trans;
>  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> -	int level = intel_ddi_level(encoder, crtc_state, 0);
>  	int n_entries, ln;
>  
>  	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
> @@ -66,6 +65,7 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
>  		return;
>  
>  	for (ln = 0; ln < 4; ln++) {
> +		int level = intel_ddi_level(encoder, crtc_state, ln);
>  		u32 val = 0;
>  
>  		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);

Re: [Intel-gfx] [PATCH 13/16] drm/i915: Use intel_de_rmw() for tgl dkl phy programming

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Streamline the code by using intel_de_rmw().

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
>  1 file changed, 16 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 85247744e9dd..3c1b289df2c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1307,7 +1307,6 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  	for (ln = 0; ln < 2; ln++) {
>  		int level;
> -		u32 val;
>  
>  		intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
>  			       HIP_INDEX_VAL(tc_port, ln));
> @@ -1316,29 +1315,26 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
>  
> -		val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
> -		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
> -			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> -			 DKL_TX_VSWING_CONTROL_MASK);
> -		val |= DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
> -			DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
> -			DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
> -		intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
> +		intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port),
> +			     DKL_TX_PRESHOOT_COEFF_MASK |
> +			     DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> +			     DKL_TX_VSWING_CONTROL_MASK,
> +			     DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
> +			     DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
> +			     DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot));
>  
>  		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
>  
> -		val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
> -		val &= ~(DKL_TX_PRESHOOT_COEFF_MASK |
> -			 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> -			 DKL_TX_VSWING_CONTROL_MASK);
> -		val |= DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
> -			DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
> -			DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot);
> -		intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
> +		intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port),
> +			     DKL_TX_PRESHOOT_COEFF_MASK |
> +			     DKL_TX_DE_EMPAHSIS_COEFF_MASK |
> +			     DKL_TX_VSWING_CONTROL_MASK,
> +			     DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing) |
> +			     DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
> +			     DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot));
>  
> -		val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
> -		val &= ~DKL_TX_DP20BITMODE;
> -		intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
> +		intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
> +			     DKL_TX_DP20BITMODE, 0);
>  	}
>  }
>  

Re: [Intel-gfx] [PATCH 14/16] drm/i915: Use intel_de_rmw() for icl mg phy programming

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Streamline the code by using intel_de_rmw().

Some lines above 100 cols, other than that:

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 111 ++++++++---------------
>  1 file changed, 39 insertions(+), 72 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3c1b289df2c0..ce8c85701cff 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1165,7 +1165,6 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
>  	const struct intel_ddi_buf_trans *trans;
>  	int n_entries, ln;
> -	u32 val;
>  
>  	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
>  		return;
> @@ -1174,15 +1173,11 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
>  		return;
>  
> -	/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
>  	for (ln = 0; ln < 2; ln++) {
> -		val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
> -		val &= ~CRI_USE_FS32;
> -		intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
> -
> -		val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
> -		val &= ~CRI_USE_FS32;
> -		intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
> +		intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
> +			     CRI_USE_FS32, 0);
> +		intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
> +			     CRI_USE_FS32, 0);
>  	}
>  
>  	/* Program MG_TX_SWINGCTRL with values from vswing table */
> @@ -1191,19 +1186,15 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
>  
> -		val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
> -		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
> -		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> -			trans->entries[level].mg.cri_txdeemph_override_17_12);
> -		intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
> +		intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
> +			     CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
> +			     CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
>  
>  		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
>  
> -		val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
> -		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
> -		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> -			trans->entries[level].mg.cri_txdeemph_override_17_12);
> -		intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
> +		intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
> +			     CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
> +			     CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
>  	}
>  
>  	/* Program MG_TX_DRVCTRL with values from vswing table */
> @@ -1212,27 +1203,21 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
>  
> -		val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
> -		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> -			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> -		val |= CRI_TXDEEMPH_OVERRIDE_5_0(
> -			trans->entries[level].mg.cri_txdeemph_override_5_0) |
> -			CRI_TXDEEMPH_OVERRIDE_11_6(
> -				trans->entries[level].mg.cri_txdeemph_override_11_6) |
> -			CRI_TXDEEMPH_OVERRIDE_EN;
> -		intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
> +		intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
> +			     CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> +			     CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
> +			     CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
> +			     CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
> +			     CRI_TXDEEMPH_OVERRIDE_EN);
>  
>  		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
>  
> -		val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
> -		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> -			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> -		val |= CRI_TXDEEMPH_OVERRIDE_5_0(
> -			trans->entries[level].mg.cri_txdeemph_override_5_0) |
> -			CRI_TXDEEMPH_OVERRIDE_11_6(
> -				trans->entries[level].mg.cri_txdeemph_override_11_6) |
> -			CRI_TXDEEMPH_OVERRIDE_EN;
> -		intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
> +		intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
> +			     CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> +			     CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
> +			     CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
> +			     CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
> +			     CRI_TXDEEMPH_OVERRIDE_EN);
>  
>  		/* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
>  	}
> @@ -1243,50 +1228,32 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  	 * values from table for which TX1 and TX2 enabled.
>  	 */
>  	for (ln = 0; ln < 2; ln++) {
> -		val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
> -		if (crtc_state->port_clock < 300000)
> -			val |= CFG_LOW_RATE_LKREN_EN;
> -		else
> -			val &= ~CFG_LOW_RATE_LKREN_EN;
> -		intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
> +		intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
> +			     CFG_LOW_RATE_LKREN_EN,
> +			     crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
>  	}
>  
>  	/* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
>  	for (ln = 0; ln < 2; ln++) {
> -		val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
> -		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
> -		if (crtc_state->port_clock <= 500000) {
> -			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
> -		} else {
> -			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
> -				CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
> -		}
> -		intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
> +		intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
> +			     CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
> +			     CFG_AMI_CK_DIV_OVERRIDE_EN,
> +			     crtc_state->port_clock > 500000 ?
> +			     CFG_AMI_CK_DIV_OVERRIDE_EN | CFG_AMI_CK_DIV_OVERRIDE_VAL(1) : 0);
>  
> -		val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
> -		val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
> -		if (crtc_state->port_clock <= 500000) {
> -			val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
> -		} else {
> -			val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
> -				CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
> -		}
> -		intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
> +		intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
> +			     CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
> +			     CFG_AMI_CK_DIV_OVERRIDE_EN,
> +			     crtc_state->port_clock > 500000 ?
> +			     CFG_AMI_CK_DIV_OVERRIDE_EN | CFG_AMI_CK_DIV_OVERRIDE_VAL(1) : 0);
>  	}
>  
>  	/* Program MG_TX_PISO_READLOAD with values from vswing table */
>  	for (ln = 0; ln < 2; ln++) {
> -		val = intel_de_read(dev_priv,
> -				    MG_TX1_PISO_READLOAD(ln, tc_port));
> -		val |= CRI_CALCINIT;
> -		intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
> -			       val);
> -
> -		val = intel_de_read(dev_priv,
> -				    MG_TX2_PISO_READLOAD(ln, tc_port));
> -		val |= CRI_CALCINIT;
> -		intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
> -			       val);
> +		intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
> +			     0, CRI_CALCINIT);
> +		intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
> +			     0, CRI_CALCINIT);
>  	}
>  }
>  

Re: [Intel-gfx] [PATCH 15/16] drm/i915: Use intel_de_rmw() for icl combo phy programming

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Streamline the code by using intel_de_rmw().

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 44 ++++++++++--------------
>  1 file changed, 18 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ce8c85701cff..c7c86b497ebc 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1070,14 +1070,11 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	for (ln = 0; ln < 4; ln++) {
>  		int level = intel_ddi_level(encoder, crtc_state, ln);
>  
> -		val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
> -		val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> -			 RCOMP_SCALAR_MASK);
> -		val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
> -		val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel);
> -		/* Program Rcomp scalar for every table entry */
> -		val |= RCOMP_SCALAR(0x98);
> -		intel_de_write(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), val);
> +		intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
> +			     SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
> +			     SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
> +			     SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
> +			     RCOMP_SCALAR(0x98));
>  	}
>  
>  	/* Program PORT_TX_DW4 */
> @@ -1085,23 +1082,20 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	for (ln = 0; ln < 4; ln++) {
>  		int level = intel_ddi_level(encoder, crtc_state, ln);
>  
> -		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> -		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> -			 CURSOR_COEFF_MASK);
> -		val |= POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1);
> -		val |= POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2);
> -		val |= CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff);
> -		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
> +		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
> +			     POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
> +			     POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
> +			     POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
> +			     CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
>  	}
>  
>  	/* Program PORT_TX_DW7 */
>  	for (ln = 0; ln < 4; ln++) {
>  		int level = intel_ddi_level(encoder, crtc_state, ln);
>  
> -		val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
> -		val &= ~N_SCALAR_MASK;
> -		val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
> -		intel_de_write(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), val);
> +		intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
> +			     N_SCALAR_MASK,
> +			     N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
>  	}
>  }
>  
> @@ -1133,16 +1127,14 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
>  	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
>  	 */
>  	for (ln = 0; ln < 4; ln++) {
> -		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> -		val &= ~LOADGEN_SELECT;
> -		val |= icl_combo_phy_loadgen_select(crtc_state, ln);
> -		intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
> +		intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
> +			     LOADGEN_SELECT,
> +			     icl_combo_phy_loadgen_select(crtc_state, ln));
>  	}
>  
>  	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
> -	val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
> -	val |= SUS_CLOCK_CONFIG;
> -	intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
> +	intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
> +		     0, SUS_CLOCK_CONFIG);
>  
>  	/* 4. Clear training enable to change swing values */
>  	val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));

Re: [Intel-gfx] [PATCH 12/16] drm/i915: Enable per-lane drive settings for icl+

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Now that the link buf_trans, link training, and the
> combo/mg/dkl/snps phy programming are all fixed up we can
> allow per-lane DP drive settings on icl+. Make it so.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 1a943ae38a6b..279371237fe9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -301,7 +301,10 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
>  static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
>  				       enum drm_dp_phy dp_phy)
>  {
> -	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy);
> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> +	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
> +		DISPLAY_VER(i915) >= 11;
>  }
>  
>  static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,

Re: [Intel-gfx] [PATCH 09/16] drm/i915: Query the vswing levels per-lane for icl mg phy

[Ville Syrjälä]

On Fri, Oct 29, 2021 at 09:59:11PM +0000, Souza, Jose wrote:
> On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Prepare for per-lane drive settings by querying the desired vswing
> > level per-lane.
> > 
> > Note that the code only does two loops, with each one writing the
> > levels for two TX lanes.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++++++++++++-
> >  1 file changed, 12 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4c400f0e7347..1874a2ca8f3b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1163,7 +1163,6 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
> > -	int level = intel_ddi_level(encoder, crtc_state, 0);
> >  	const struct intel_ddi_buf_trans *trans;
> >  	int n_entries, ln;
> >  	u32 val;
> > @@ -1188,12 +1187,18 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
> >  
> >  	/* Program MG_TX_SWINGCTRL with values from vswing table */
> >  	for (ln = 0; ln < 2; ln++) {
> > +		int level;
> > +
> > +		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
> > +
> >  		val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
> >  		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
> >  		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> >  			trans->entries[level].mg.cri_txdeemph_override_17_12);
> >  		intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
> >  
> > +		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
> > +
> >  		val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
> >  		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
> >  		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> > @@ -1203,6 +1208,10 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
> >  
> >  	/* Program MG_TX_DRVCTRL with values from vswing table */
> >  	for (ln = 0; ln < 2; ln++) {
> > +		int level;
> > +
> > +		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
> > +
> >  		val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
> >  		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> >  			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> > @@ -1213,6 +1222,8 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
> >  			CRI_TXDEEMPH_OVERRIDE_EN;
> >  		intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
> >  
> > +		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
> 
> I believe our code style requires that we have spaces, so it should be (2 * ln + 1).

Neither is really good, but the one with spaces just looks ugly IMO.

> 
> With the answers requested in the previous patch:
> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> 
> 
> > +
> >  		val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
> >  		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
> >  			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> 

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 08/16] drm/i915: Query the vswing levels per-lane for icl combo phy

[Ville Syrjälä]

On Fri, Oct 29, 2021 at 09:57:02PM +0000, Souza, Jose wrote:
> On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Prepare for per-lane drive settings by querying the desired vswing
> > level per-lane.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index aa789cabc55b..4c400f0e7347 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1039,7 +1039,6 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> >  					 const struct intel_crtc_state *crtc_state)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > -	int level = intel_ddi_level(encoder, crtc_state, 0);
> >  	const struct intel_ddi_buf_trans *trans;
> >  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> >  	int n_entries, ln;
> > @@ -1069,6 +1068,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> >  
> >  	/* Program PORT_TX_DW2 */
> >  	for (ln = 0; ln < 4; ln++) {
> > +		int level = intel_ddi_level(encoder, crtc_state, ln);
> > +
> >  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
> >  		val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> >  			 RCOMP_SCALAR_MASK);
> > @@ -1082,6 +1083,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> >  	/* Program PORT_TX_DW4 */
> >  	/* We cannot write to GRP. It would overwrite individual loadgen. */
> >  	for (ln = 0; ln < 4; ln++) {
> > +		int level = intel_ddi_level(encoder, crtc_state, ln);
> > +
> >  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> >  		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> >  			 CURSOR_COEFF_MASK);
> > @@ -1093,6 +1096,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> >  
> >  	/* Program PORT_TX_DW7 */
> >  	for (ln = 0; ln < 4; ln++) {
> > +		int level = intel_ddi_level(encoder, crtc_state, ln);
> > +
> >  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
> >  		val &= ~N_SCALAR_MASK;
> >  		val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
> 
> The cover letter or one of the earlier patches should have some explanation about the reasons of this the group to lane conversion.

They do say it's for per-lane drive setings. Not rally sure what to add
to that.

> Reading one of the later patches I understood is because DP 2.0 allows different level per lane but would be nice to know for sure the reason.

It has always been a feature of DP, we just never implemented it for
whatever reason.

> 
> What if it is only using 2 lanes? Programming disabled lanes will cause any issue?

Depends on whether the registers are available or not. For CHV I know
the unused lanes will be fully powered off and you can't actually access
the registers (and vlv_dpio_read() will actually WARN when it sees the
~0 value from an inaccessible register). For later platforms I don't
actually know what happens. We don't have an equivalent of that CHV WARN
but I would hope that we'd get an unclaimed reg warning if the register
is inaccessible.

Although I suppose there's isn't any real harm in poking inaccssible
registers. The reads should just return all 0s or all 1s, and the
writes go to /dev/null.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 08/16] drm/i915: Query the vswing levels per-lane for icl combo phy

[Souza, Jose]

On Mon, 2021-11-01 at 12:11 +0200, Ville Syrjälä wrote:
> On Fri, Oct 29, 2021 at 09:57:02PM +0000, Souza, Jose wrote:
> > On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Prepare for per-lane drive settings by querying the desired vswing
> > > level per-lane.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++++++-
> > >  1 file changed, 6 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index aa789cabc55b..4c400f0e7347 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -1039,7 +1039,6 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> > >  					 const struct intel_crtc_state *crtc_state)
> > >  {
> > >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > -	int level = intel_ddi_level(encoder, crtc_state, 0);
> > >  	const struct intel_ddi_buf_trans *trans;
> > >  	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> > >  	int n_entries, ln;
> > > @@ -1069,6 +1068,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> > >  
> > >  	/* Program PORT_TX_DW2 */
> > >  	for (ln = 0; ln < 4; ln++) {
> > > +		int level = intel_ddi_level(encoder, crtc_state, ln);
> > > +
> > >  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
> > >  		val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> > >  			 RCOMP_SCALAR_MASK);
> > > @@ -1082,6 +1083,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> > >  	/* Program PORT_TX_DW4 */
> > >  	/* We cannot write to GRP. It would overwrite individual loadgen. */
> > >  	for (ln = 0; ln < 4; ln++) {
> > > +		int level = intel_ddi_level(encoder, crtc_state, ln);
> > > +
> > >  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
> > >  		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> > >  			 CURSOR_COEFF_MASK);
> > > @@ -1093,6 +1096,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> > >  
> > >  	/* Program PORT_TX_DW7 */
> > >  	for (ln = 0; ln < 4; ln++) {
> > > +		int level = intel_ddi_level(encoder, crtc_state, ln);
> > > +
> > >  		val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
> > >  		val &= ~N_SCALAR_MASK;
> > >  		val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
> > 
> > The cover letter or one of the earlier patches should have some explanation about the reasons of this the group to lane conversion.
> 
> They do say it's for per-lane drive setings. Not rally sure what to add
> to that.
> 
> > Reading one of the later patches I understood is because DP 2.0 allows different level per lane but would be nice to know for sure the reason.
> 
> It has always been a feature of DP, we just never implemented it for
> whatever reason.
> 
> > 
> > What if it is only using 2 lanes? Programming disabled lanes will cause any issue?
> 
> Depends on whether the registers are available or not. For CHV I know
> the unused lanes will be fully powered off and you can't actually access
> the registers (and vlv_dpio_read() will actually WARN when it sees the
> ~0 value from an inaccessible register). For later platforms I don't
> actually know what happens. We don't have an equivalent of that CHV WARN
> but I would hope that we'd get an unclaimed reg warning if the register
> is inaccessible.
> 
> Although I suppose there's isn't any real harm in poking inaccssible
> registers. The reads should just return all 0s or all 1s, and the
> writes go to /dev/null.
> 

Fair enough.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>