From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52B07C11F66 for ; Tue, 29 Jun 2021 13:47:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A17B61D8B for ; Tue, 29 Jun 2021 13:47:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234163AbhF2Ntc (ORCPT ); Tue, 29 Jun 2021 09:49:32 -0400 Received: from mail.kernel.org ([198.145.29.99]:60264 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233050AbhF2Ntb (ORCPT ); Tue, 29 Jun 2021 09:49:31 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id AD3D661D94; Tue, 29 Jun 2021 13:47:04 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1lyE4s-00Adto-On; Tue, 29 Jun 2021 14:47:02 +0100 Date: Tue, 29 Jun 2021 14:47:02 +0100 Message-ID: <877dicbx61.wl-maz@kernel.org> From: Marc Zyngier To: Alexandre Chartre Cc: will@kernel.org, catalin.marinas@arm.com, alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, konrad.wilk@oracle.com Subject: Re: [PATCH] KVM: arm64: Disabling disabled PMU counters wastes a lot of time In-Reply-To: References: <20210628161925.401343-1-alexandre.chartre@oracle.com> <878s2tavks.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandre.chartre@oracle.com, will@kernel.org, catalin.marinas@arm.com, alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, konrad.wilk@oracle.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On Tue, 29 Jun 2021 14:16:55 +0100, Alexandre Chartre wrote: > > > Hi Marc, > > On 6/29/21 11:06 AM, Marc Zyngier wrote: > > Hi Alexandre, [...] > > So the sysreg is the only thing we should consider, and I think we > > should drop the useless masking. There is at least another instance of > > this in the PMU code (kvm_pmu_overflow_status()), and apart from > > kvm_pmu_vcpu_reset(), only the sysreg accessors should care about the > > masking to sanitise accesses. > > > > What do you think? > > > > I think you are right. PMCNTENSET_EL0 is already masked with > kvm_pmu_valid_counter_mask() so there's effectively no need to mask > it again when we use it. I will send an additional patch (on top of > this one) to remove useless masking. Basically, changes would be: > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index bab4b735a0cf..e0dfd7ce4ba0 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -373,7 +373,6 @@ static u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcpu) > reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); > reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); > reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1); > - reg &= kvm_pmu_valid_counter_mask(vcpu); > } > return reg; > @@ -564,21 +563,22 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) > */ > void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) > { > - unsigned long mask = kvm_pmu_valid_counter_mask(vcpu); > + unsigned long mask; > int i; > if (val & ARMV8_PMU_PMCR_E) { > kvm_pmu_enable_counter_mask(vcpu, > - __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask); > + __vcpu_sys_reg(vcpu, PMCNTENSET_EL0)); > } else { > kvm_pmu_disable_counter_mask(vcpu, > - __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask); > + __vcpu_sys_reg(vcpu, PMCNTENSET_EL0)); > } > if (val & ARMV8_PMU_PMCR_C) > kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0); > if (val & ARMV8_PMU_PMCR_P) { > + mask = kvm_pmu_valid_counter_mask(vcpu); Careful here, this clashes with a fix from Alexandru that is currently in -next (PMCR_EL0.P shouldn't reset the cycle counter) and aimed at 5.14. And whilst you're at it, consider moving the 'mask' declaration here too. > for_each_set_bit(i, &mask, 32) > kvm_pmu_set_counter_value(vcpu, i, 0); > } > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 1a7968ad078c..2e406905760e 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -845,7 +845,7 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > kvm_pmu_disable_counter_mask(vcpu, val); > } > } else { > - p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; > + p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); > } > return true; If you are cleaning up the read-side of sysregs, access_pminten() and access_pmovs() could have some of your attention too. Thanks, M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F40EC11F66 for ; Tue, 29 Jun 2021 13:47:10 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id DE85A61DC2 for ; Tue, 29 Jun 2021 13:47:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DE85A61DC2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 7D4324A1A5; Tue, 29 Jun 2021 09:47:09 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VZxcRK5B0BOp; Tue, 29 Jun 2021 09:47:08 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 55B9D40870; Tue, 29 Jun 2021 09:47:08 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 1C024407ED for ; Tue, 29 Jun 2021 09:47:07 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BfEZThqjWhmM for ; Tue, 29 Jun 2021 09:47:06 -0400 (EDT) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id D7A0340630 for ; Tue, 29 Jun 2021 09:47:05 -0400 (EDT) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id AD3D661D94; Tue, 29 Jun 2021 13:47:04 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1lyE4s-00Adto-On; Tue, 29 Jun 2021 14:47:02 +0100 Date: Tue, 29 Jun 2021 14:47:02 +0100 Message-ID: <877dicbx61.wl-maz@kernel.org> From: Marc Zyngier To: Alexandre Chartre Subject: Re: [PATCH] KVM: arm64: Disabling disabled PMU counters wastes a lot of time In-Reply-To: References: <20210628161925.401343-1-alexandre.chartre@oracle.com> <878s2tavks.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandre.chartre@oracle.com, will@kernel.org, catalin.marinas@arm.com, alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, konrad.wilk@oracle.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, catalin.marinas@arm.com, konrad.wilk@oracle.com, will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Tue, 29 Jun 2021 14:16:55 +0100, Alexandre Chartre wrote: > > > Hi Marc, > > On 6/29/21 11:06 AM, Marc Zyngier wrote: > > Hi Alexandre, [...] > > So the sysreg is the only thing we should consider, and I think we > > should drop the useless masking. There is at least another instance of > > this in the PMU code (kvm_pmu_overflow_status()), and apart from > > kvm_pmu_vcpu_reset(), only the sysreg accessors should care about the > > masking to sanitise accesses. > > > > What do you think? > > > > I think you are right. PMCNTENSET_EL0 is already masked with > kvm_pmu_valid_counter_mask() so there's effectively no need to mask > it again when we use it. I will send an additional patch (on top of > this one) to remove useless masking. Basically, changes would be: > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index bab4b735a0cf..e0dfd7ce4ba0 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -373,7 +373,6 @@ static u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcpu) > reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); > reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); > reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1); > - reg &= kvm_pmu_valid_counter_mask(vcpu); > } > return reg; > @@ -564,21 +563,22 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) > */ > void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) > { > - unsigned long mask = kvm_pmu_valid_counter_mask(vcpu); > + unsigned long mask; > int i; > if (val & ARMV8_PMU_PMCR_E) { > kvm_pmu_enable_counter_mask(vcpu, > - __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask); > + __vcpu_sys_reg(vcpu, PMCNTENSET_EL0)); > } else { > kvm_pmu_disable_counter_mask(vcpu, > - __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask); > + __vcpu_sys_reg(vcpu, PMCNTENSET_EL0)); > } > if (val & ARMV8_PMU_PMCR_C) > kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0); > if (val & ARMV8_PMU_PMCR_P) { > + mask = kvm_pmu_valid_counter_mask(vcpu); Careful here, this clashes with a fix from Alexandru that is currently in -next (PMCR_EL0.P shouldn't reset the cycle counter) and aimed at 5.14. And whilst you're at it, consider moving the 'mask' declaration here too. > for_each_set_bit(i, &mask, 32) > kvm_pmu_set_counter_value(vcpu, i, 0); > } > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 1a7968ad078c..2e406905760e 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -845,7 +845,7 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > kvm_pmu_disable_counter_mask(vcpu, val); > } > } else { > - p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; > + p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); > } > return true; If you are cleaning up the read-side of sysregs, access_pminten() and access_pmovs() could have some of your attention too. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4576AC11F66 for ; Tue, 29 Jun 2021 13:48:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1197C61D9A for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyE50-00B9in-6B; Tue, 29 Jun 2021 13:47:10 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lyE4w-00B9hA-D4 for linux-arm-kernel@lists.infradead.org; Tue, 29 Jun 2021 13:47:07 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id AD3D661D94; Tue, 29 Jun 2021 13:47:04 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1lyE4s-00Adto-On; Tue, 29 Jun 2021 14:47:02 +0100 Date: Tue, 29 Jun 2021 14:47:02 +0100 Message-ID: <877dicbx61.wl-maz@kernel.org> From: Marc Zyngier To: Alexandre Chartre Cc: will@kernel.org, catalin.marinas@arm.com, alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, konrad.wilk@oracle.com Subject: Re: [PATCH] KVM: arm64: Disabling disabled PMU counters wastes a lot of time In-Reply-To: References: <20210628161925.401343-1-alexandre.chartre@oracle.com> <878s2tavks.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandre.chartre@oracle.com, will@kernel.org, catalin.marinas@arm.com, alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, konrad.wilk@oracle.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210629_064706_516460_A15A6BCE X-CRM114-Status: GOOD ( 30.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 29 Jun 2021 14:16:55 +0100, Alexandre Chartre wrote: > > > Hi Marc, > > On 6/29/21 11:06 AM, Marc Zyngier wrote: > > Hi Alexandre, [...] > > So the sysreg is the only thing we should consider, and I think we > > should drop the useless masking. There is at least another instance of > > this in the PMU code (kvm_pmu_overflow_status()), and apart from > > kvm_pmu_vcpu_reset(), only the sysreg accessors should care about the > > masking to sanitise accesses. > > > > What do you think? > > > > I think you are right. PMCNTENSET_EL0 is already masked with > kvm_pmu_valid_counter_mask() so there's effectively no need to mask > it again when we use it. I will send an additional patch (on top of > this one) to remove useless masking. Basically, changes would be: > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index bab4b735a0cf..e0dfd7ce4ba0 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -373,7 +373,6 @@ static u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcpu) > reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0); > reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); > reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1); > - reg &= kvm_pmu_valid_counter_mask(vcpu); > } > return reg; > @@ -564,21 +563,22 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) > */ > void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) > { > - unsigned long mask = kvm_pmu_valid_counter_mask(vcpu); > + unsigned long mask; > int i; > if (val & ARMV8_PMU_PMCR_E) { > kvm_pmu_enable_counter_mask(vcpu, > - __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask); > + __vcpu_sys_reg(vcpu, PMCNTENSET_EL0)); > } else { > kvm_pmu_disable_counter_mask(vcpu, > - __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask); > + __vcpu_sys_reg(vcpu, PMCNTENSET_EL0)); > } > if (val & ARMV8_PMU_PMCR_C) > kvm_pmu_set_counter_value(vcpu, ARMV8_PMU_CYCLE_IDX, 0); > if (val & ARMV8_PMU_PMCR_P) { > + mask = kvm_pmu_valid_counter_mask(vcpu); Careful here, this clashes with a fix from Alexandru that is currently in -next (PMCR_EL0.P shouldn't reset the cycle counter) and aimed at 5.14. And whilst you're at it, consider moving the 'mask' declaration here too. > for_each_set_bit(i, &mask, 32) > kvm_pmu_set_counter_value(vcpu, i, 0); > } > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 1a7968ad078c..2e406905760e 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -845,7 +845,7 @@ static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > kvm_pmu_disable_counter_mask(vcpu, val); > } > } else { > - p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; > + p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); > } > return true; If you are cleaning up the read-side of sysregs, access_pminten() and access_pmovs() could have some of your attention too. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel