From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4E7BC38A02 for ; Mon, 31 Oct 2022 05:19:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E824210E115; Mon, 31 Oct 2022 05:19:20 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id C70A110E115 for ; Mon, 31 Oct 2022 05:19:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667193555; x=1698729555; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=ukTNq33pRZiR8bexSpNPZnCDhKFfl8DCUZRDcjkPPCM=; b=j13QOxzX/BzNT4jaIqSLGIpr71FzOiBGxkRinXuBzDspJdhkGu91C7v3 1QlqMrT/4O1N7TW+r3O+aWIOYpQbSYdDRaPUO3NKjHqX4I216ajwZDi7p jLJpbxDuAVuR3brP76yqruEUabGhEmjGvEroZniVmQZP2reAIsB7Vz2vs kEpU/LH8W/rAIQLfZmOvfpKxmGktlszZdxhhZwhK/et9PRQ7C8NvwJ7HN 8LuSLPN8gMABUPXLZLPY6zH9jG1LTZPbO6Cyrw/2EATiHgtgLIhQBp79o Dydt1bdd8iiJwyR/QQQf+PFb/XXrOi3xT8TjBjUkjeWvGk2jzyOXz5Bkk Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10516"; a="373028442" X-IronPort-AV: E=Sophos;i="5.95,227,1661842800"; d="scan'208";a="373028442" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2022 22:19:14 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10516"; a="635923857" X-IronPort-AV: E=Sophos;i="5.95,227,1661842800"; d="scan'208";a="635923857" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.125.166]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2022 22:19:14 -0700 Date: Sun, 30 Oct 2022 22:19:13 -0700 Message-ID: <878rkwefji.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Gwan-gyeong Mun In-Reply-To: <20221029044230.32128-1-gwan-gyeong.mun@intel.com> References: <20221024210953.1572998-1-gwan-gyeong.mun@intel.com> <20221029044230.32128-1-gwan-gyeong.mun@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/hwmon: Fix a build error used with clang compiler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 28 Oct 2022 21:42:30 -0700, Gwan-gyeong Mun wrote: > > diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c > index 9e9781493025..c588a17f97e9 100644 > --- a/drivers/gpu/drm/i915/i915_hwmon.c > +++ b/drivers/gpu/drm/i915/i915_hwmon.c > @@ -101,21 +101,16 @@ hwm_field_read_and_scale(struct hwm_drvdata *ddat, i915_reg_t rgadr, > > static void > hwm_field_scale_and_write(struct hwm_drvdata *ddat, i915_reg_t rgadr, > - u32 field_msk, int nshift, > - unsigned int scale_factor, long lval) > + int nshift, unsigned int scale_factor, long lval) > { > u32 nval; > - u32 bits_to_clear; > - u32 bits_to_set; > > /* Computation in 64-bits to avoid overflow. Round to nearest. */ > nval = DIV_ROUND_CLOSEST_ULL((u64)lval << nshift, scale_factor); > > - bits_to_clear = field_msk; > - bits_to_set = FIELD_PREP(field_msk, nval); > - > hwm_locked_with_pm_intel_uncore_rmw(ddat, rgadr, > - bits_to_clear, bits_to_set); > + PKG_PWR_LIM_1, > + REG_FIELD_PREP(PKG_PWR_LIM_1, nval)); I registered my objection to this patch already here: https://lore.kernel.org/intel-gfx/87ilk7pwrw.wl-ashutosh.dixit@intel.com/ the crux of which is "hwm_field_scale_and_write() pairs with hwm_field_read_and_scale() (they are basically a set/get pair) so it is desirable they have identical arguments. This patch breaks that symmetry". We can merge this patch now but the moment a second caller of hwm_field_scale_and_write arrives this patch will need to be reverted. I have also posted my preferred way (as I previously indiecated) of fixing this issue here (if this needs to be fixed in i915): https://patchwork.freedesktop.org/series/110301/ IMO it would be a mistake to use REG_FIELD_PREP or FIELD_PREP here since here the mask comes in as a function argument whereas REG_FIELD_PREP and FIELD_PREP require that mask to be a compile time constant. Thanks. -- Ashutosh