From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 903C0C433EF for ; Thu, 6 Jan 2022 15:55:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240811AbiAFPzU (ORCPT ); Thu, 6 Jan 2022 10:55:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240758AbiAFPzR (ORCPT ); Thu, 6 Jan 2022 10:55:17 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9AB1C061245; Thu, 6 Jan 2022 07:55:16 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 72406B82254; Thu, 6 Jan 2022 15:55:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 04C32C36AE3; Thu, 6 Jan 2022 15:55:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1641484514; bh=3/JjCl/b4dH7CWdXSXMTGTFNWCV+HFB2frmcqgEHIyA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=d/k4oDKDjX++fwj90Nl6WbC7M3KWufTfX4TZ3KoJurpe7Pu2F9r0wWbyi6PlvNMtI Kr5aclu5PiTMkghqht6Mqjn7S3lJRic+TV4l6CJTElF4UBQu7h7wqRm0SYrHKm2x1A WfL9vC60SmZaotp/W/znVuvA8+16RsKJCTnoMVVUvy/OplOC/F7TJdJCqSN+E7C+sN NeNACVOvxPGW4C7+OweZ9jsDAZm3S5uoZkQWCzw9d8uXreTYi6K8ytFm5MKFQSdEzL sKRr1yB+0hcfQ5B2YA8K4FqUSs3DKVCMiwjX0MNxTtf9bA8JY8EQIRZ2saAQBkkiKE d51BkTuHyCX5Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1n5V6d-00GNij-Uz; Thu, 06 Jan 2022 15:55:12 +0000 Date: Thu, 06 Jan 2022 15:55:11 +0000 Message-ID: <878rvsvoyo.wl-maz@kernel.org> From: Marc Zyngier To: Pali =?UTF-8?B?Um9ow6Fy?= Cc: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Thomas Petazzoni , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Marek =?UTF-8?B?QmVow7pu?= , Russell King , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts In-Reply-To: <20220106154447.aie6taiuvav5wu6y@pali> References: <20220105150239.9628-1-pali@kernel.org> <20220105150239.9628-11-pali@kernel.org> <87bl0ovq7f.wl-maz@kernel.org> <20220106154447.aie6taiuvav5wu6y@pali> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: pali@kernel.org, lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh+dt@kernel.org, thomas.petazzoni@bootlin.com, kw@linux.com, kabel@kernel.org, rmk+kernel@armlinux.org.uk, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 06 Jan 2022 15:44:47 +0000, Pali Roh=C3=A1r wrote: >=20 > On Thursday 06 January 2022 15:28:20 Marc Zyngier wrote: > > On Wed, 05 Jan 2022 15:02:38 +0000, > > Pali Roh=C3=A1r wrote: > > >=20 > > > This adds support for legacy INTx interrupts received from other PCIe > > > devices and which are reported by a new INTx irq chip. > > >=20 > > > With this change, kernel can distinguish between INTA, INTB, INTC and= INTD > > > interrupts. > > >=20 > > > Note that for this support, device tree files has to be properly adju= sted > > > to provide "interrupts" or "interrupts-extended" property with intx > > > interrupt source, "interrupt-names" property with "intx" string and a= lso > > > 'interrupt-controller' subnode must be defined. > > >=20 > > > If device tree files do not provide these nodes then driver would wor= k as > > > before. > > >=20 > > > Signed-off-by: Pali Roh=C3=A1r > > > --- > > > drivers/pci/controller/pci-mvebu.c | 182 +++++++++++++++++++++++++++= -- > > > 1 file changed, 174 insertions(+), 8 deletions(-) > > >=20 > > > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/control= ler/pci-mvebu.c > > > index 1e90ab888075..04bcdd7b7a6d 100644 > > > --- a/drivers/pci/controller/pci-mvebu.c > > > +++ b/drivers/pci/controller/pci-mvebu.c > > > @@ -54,9 +54,10 @@ > > > PCIE_CONF_ADDR_EN) > > > #define PCIE_CONF_DATA_OFF 0x18fc > > > #define PCIE_INT_CAUSE_OFF 0x1900 > > > +#define PCIE_INT_UNMASK_OFF 0x1910 > > > +#define PCIE_INT_INTX(i) BIT(24+i) > > > #define PCIE_INT_PM_PME BIT(28) > > > -#define PCIE_MASK_OFF 0x1910 > > > -#define PCIE_MASK_ENABLE_INTS 0x0f000000 > > > +#define PCIE_INT_ALL_MASK GENMASK(31, 0) > > > #define PCIE_CTRL_OFF 0x1a00 > > > #define PCIE_CTRL_X1_MODE 0x0001 > > > #define PCIE_CTRL_RC_MODE BIT(1) > > > @@ -110,6 +111,10 @@ struct mvebu_pcie_port { > > > struct mvebu_pcie_window iowin; > > > u32 saved_pcie_stat; > > > struct resource regs; > > > + struct irq_domain *intx_irq_domain; > > > + struct irq_chip intx_irq_chip; > >=20 > > Why is this structure per port? It really should be global. Printing > > the port number in the name isn't enough of a reason. >=20 > Because each port has its own independent set of INTA-INTD > interrupts. That doesn't warrant a copy of an irq_chip structure that contains the exact same callbacks, and only differs by *a string*. And the use of this string is only to end-up in /proc/interrupts, which is totally pointless. >=20 > > > + raw_spinlock_t irq_lock; > > > + int intx_irq; > > > }; > > > =20 > > > static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 va= l, u32 reg) > > > @@ -235,7 +240,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pc= ie_port *port) > > > =20 > > > static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) > > > { > > > - u32 ctrl, lnkcap, cmd, dev_rev, mask; > > > + u32 ctrl, lnkcap, cmd, dev_rev, unmask; > > > =20 > > > /* Setup PCIe controller to Root Complex mode. */ > > > ctrl =3D mvebu_readl(port, PCIE_CTRL_OFF); > > > @@ -288,10 +293,30 @@ static void mvebu_pcie_setup_hw(struct mvebu_pc= ie_port *port) > > > /* Point PCIe unit MBUS decode windows to DRAM space. */ > > > mvebu_pcie_setup_wins(port); > > > =20 > > > - /* Enable interrupt lines A-D. */ > > > - mask =3D mvebu_readl(port, PCIE_MASK_OFF); > > > - mask |=3D PCIE_MASK_ENABLE_INTS; > > > - mvebu_writel(port, mask, PCIE_MASK_OFF); > > > + /* Mask all interrupt sources. */ > > > + mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF); > > > + > > > + /* Clear all interrupt causes. */ > > > + mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF); > > > + > > > + if (port->intx_irq <=3D 0) { > > > + /* > > > + * When neither "summary" interrupt, nor "intx" interrupt was > > > + * specified in DT then unmask all legacy INTx interrupts as in > > > + * this case driver does not provide a way for masking and > > > + * unmasking of individual legacy INTx interrupts. In this case > > > + * all interrupts, including legacy INTx are reported via one > > > + * shared GIC source and therefore kernel cannot distinguish > > > + * which individual legacy INTx was triggered. These interrupts > > > + * are shared, so it should not cause any issue. Just > > > + * performance penalty as every PCIe interrupt handler needs to > > > + * be called when some interrupt is triggered. > > > + */ > > > + unmask =3D mvebu_readl(port, PCIE_INT_UNMASK_OFF); > > > + unmask |=3D PCIE_INT_INTX(0) | PCIE_INT_INTX(1) | > > > + PCIE_INT_INTX(2) | PCIE_INT_INTX(3); > > > + mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); > >=20 > > Maybe worth printing a warning here, so that the user knows they are > > on thin ice. >=20 > Ok. I can add it here. Anyway, this is default current state without > this patch. >=20 > > > + } > > > } > > > =20 > > > static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pci= e *pcie, > > > @@ -924,6 +949,109 @@ static struct pci_ops mvebu_pcie_ops =3D { > > > .write =3D mvebu_pcie_wr_conf, > > > }; > > > =20 > > > +static void mvebu_pcie_intx_irq_mask(struct irq_data *d) > > > +{ > > > + struct mvebu_pcie_port *port =3D d->domain->host_data; > > > + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); > > > + unsigned long flags; > > > + u32 unmask; > > > + > > > + raw_spin_lock_irqsave(&port->irq_lock, flags); > > > + unmask =3D mvebu_readl(port, PCIE_INT_UNMASK_OFF); > > > + unmask &=3D ~PCIE_INT_INTX(hwirq); > > > + mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); > > > + raw_spin_unlock_irqrestore(&port->irq_lock, flags); > > > +} > > > + > > > +static void mvebu_pcie_intx_irq_unmask(struct irq_data *d) > > > +{ > > > + struct mvebu_pcie_port *port =3D d->domain->host_data; > > > + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); > > > + unsigned long flags; > > > + u32 unmask; > > > + > > > + raw_spin_lock_irqsave(&port->irq_lock, flags); > > > + unmask =3D mvebu_readl(port, PCIE_INT_UNMASK_OFF); > > > + unmask |=3D PCIE_INT_INTX(hwirq); > > > + mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); > > > + raw_spin_unlock_irqrestore(&port->irq_lock, flags); > > > +} > > > + > > > +static int mvebu_pcie_intx_irq_map(struct irq_domain *h, > > > + unsigned int virq, irq_hw_number_t hwirq) > > > +{ > > > + struct mvebu_pcie_port *port =3D h->host_data; > > > + > > > + irq_set_status_flags(virq, IRQ_LEVEL); > > > + irq_set_chip_and_handler(virq, &port->intx_irq_chip, handle_level_i= rq); > > > + irq_set_chip_data(virq, port); > > > + > > > + return 0; > > > +} > > > + > > > +static const struct irq_domain_ops mvebu_pcie_intx_irq_domain_ops = =3D { > > > + .map =3D mvebu_pcie_intx_irq_map, > > > + .xlate =3D irq_domain_xlate_onecell, > > > +}; > > > + > > > +static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port) > > > +{ > > > + struct device *dev =3D &port->pcie->pdev->dev; > > > + struct device_node *pcie_intc_node; > > > + > > > + raw_spin_lock_init(&port->irq_lock); > > > + > > > + port->intx_irq_chip.name =3D devm_kasprintf(dev, GFP_KERNEL, > > > + "mvebu-%s-INTx", > > > + port->name); > >=20 > > That's exactly what I really don't want to see. It prevents sharing of > > the irq_chip structure, and gets in the way of making it const in the > > future. Yes, I know that some drivers do that. I can't fix those, > > because /proc/interrupts is ABI. But I really don't want to see more > > of these. >=20 > Well, I do not understand why it should be shared and with who. HW has N > independent IRQ chips for legacy interrupts. And each one will be > specified in DT per HW layout / design. If you have multiple ports, all the ports can share the irq_chip structure. Actually scratch that. They *MUST* share the structure. The only reason you're not sharing it is to be able to print this useless string in /proc/interrupts. M. --=20 Without deviation from the norm, progress is not possible. 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<878rvsvoyo.wl-maz@kernel.org> From: Marc Zyngier To: Pali =?UTF-8?B?Um9ow6Fy?= Cc: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Thomas Petazzoni , Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= , Marek =?UTF-8?B?QmVow7pu?= , Russell King , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 10/11] PCI: mvebu: Implement support for legacy INTx interrupts In-Reply-To: <20220106154447.aie6taiuvav5wu6y@pali> References: <20220105150239.9628-1-pali@kernel.org> <20220105150239.9628-11-pali@kernel.org> <87bl0ovq7f.wl-maz@kernel.org> <20220106154447.aie6taiuvav5wu6y@pali> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: pali@kernel.org, lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh+dt@kernel.org, thomas.petazzoni@bootlin.com, kw@linux.com, kabel@kernel.org, rmk+kernel@armlinux.org.uk, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220106_075515_556802_3949EE67 X-CRM114-Status: GOOD ( 49.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCAwNiBKYW4gMjAyMiAxNTo0NDo0NyArMDAwMCwKUGFsaSBSb2jDoXIgPHBhbGlAa2Vy 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