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[91.155.214.58]) by smtp.gmail.com with ESMTPSA id r11sm6559950lfc.29.2020.06.25.23.52.12 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 Jun 2020 23:52:13 -0700 (PDT) From: Felipe Balbi To: Pawel Laszczak , gregkh@linuxfoundation.org, robh+dt@kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: dan.carpenter@oracle.com, ben.dooks@codethink.co.uk, colin.king@canonical.com, rogerq@ti.com, peter.chen@nxp.com, weiyongjun1@huawei.com, jpawar@cadence.com, kurahul@cadene.com, sparmar@cadence.com, Pawel Laszczak Subject: Re: [PATCH RFC 0/5] Introduced new Cadence USBSSP DRD Driver. In-Reply-To: <20200626045450.10205-1-pawell@cadence.com> References: <20200626045450.10205-1-pawell@cadence.com> Date: Fri, 26 Jun 2020 09:52:08 +0300 Message-ID: <878sga5nfr.fsf@kernel.org> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable Hi, Pawel Laszczak writes: > This patch introduce new Cadence USBSS DRD driver to linux kernel. > > The Cadence USBSS DRD Controller is a highly configurable IP Core which > can be instantiated as Dual-Role Device (DRD), Peripheral Only and > Host Only (XHCI)configurations. > > The current driver has been validated with FPGA burned. We have support > for PCIe bus, which is used on FPGA prototyping. > > The host side of USBSS-DRD controller is compliance with XHCI > specification, so it works with standard XHCI Linux driver. > > The host side of USBSS DRD controller is compliant with XHCI. > The architecture for device side is almost the same as for host side, > and most of the XHCI specification can be used to understand how > this controller operates. > > This controller and driver support Full Speed, Hight Speed, Supper Speed > and Supper Speed Plus USB protocol. > > The prefix cdnsp used in driver has chosen by analogy to cdn3 driver. > The last letter of this acronym means PLUS. The formal name of controller > is USBSSP but it's to generic so I've decided to use CDNSP. > > The patch 1: adds DT binding. > The patch 2: adds PCI to platform wrapper used on Cadnece testing > platform. It is FPGA based on platform. > The patches 3-5: add the main part of driver and has been intentionally > split into 3 part. In my opinion such division should not > affect understanding and reviewing the driver, and cause that > main patch (4/5) is little smaller. Patch 3 introduces main > header file for driver, 4 is the main part that implements a= ll > functionality of driver and 5 introduces tracepoints. I'm more interested in how is this different from CDNS3. Aren't they SW com= patible? =2D-=20 balbi --=-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEElLzh7wn96CXwjh2IzL64meEamQYFAl71mxgACgkQzL64meEa mQaiPQ//a7Zb3mi4EERXBszW7rCLKyFOdQYjy83WFHOxrAV/iXqGsx6KARPngoDg 1u8cCOef0xdHjXt8aP9BhD9n2yvSb0oIMZFcyw/BOPADEUN9OBqCVxWSLDTZ1YuX O6n61nGDVkC/WWqwoiE/+yXV1MvEPV1nH/RQlh8aJa5WXe2CglkmKEJJC/Wo83BO Q+tsXgN1BCUAGl8TILSlrWjaP9jSQINFuzyU+fqJs6nzI/vnxMSvCk00UEwOQVMa HXLftoVdg9q9i4fphnW0hAj80bSG4i6U9r7cH2Ne+0QZzkSv4FFaKs3AutA9il1Z tL88XIvUx5fXy7vfBJL+P4HY5IfbP42jVKvMrjA+A2wdI0IRhGAvZKFnuZV2B2Ad FswDnFwUXvY8PmWS9/JFKC/Xqharmo6+9ozS9KZpzFMgDJtWA31fRwrSrxFx56Lo JhJfzy5awku/qNSQgh48tfyaat28Ubj3PjHe6UDe6PCq4zcrwOfobdCb0CNroWoQ gG94c2i4cGbHRKSWhBYGkz11U5TN5KfArKR/oPiCc3O8BPoOj9nru+j559cHr34J Gt2ToK0H/ICL+OLyqkuEMu0CERM9JpDzYhytaC+VxJbvYBDV9GzO//nqNnJyLFNm gQzfbcNSALJJGNIB7grpjCMeqOYT588o0rF79MitN94HpHYFWuk= =ZsUv -----END PGP SIGNATURE----- --=-=-=--