From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56123) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c9myy-0006LB-IQ for qemu-devel@nongnu.org; Thu, 24 Nov 2016 00:54:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c9myv-0001vD-Dk for qemu-devel@nongnu.org; Thu, 24 Nov 2016 00:54:04 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:39406 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c9myv-0001uk-7g for qemu-devel@nongnu.org; Thu, 24 Nov 2016 00:54:01 -0500 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uAO5risb037106 for ; Thu, 24 Nov 2016 00:53:59 -0500 Received: from e28smtp04.in.ibm.com (e28smtp04.in.ibm.com [125.16.236.4]) by mx0b-001b2d01.pphosted.com with ESMTP id 26wrd4aqpc-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 24 Nov 2016 00:53:59 -0500 Received: from localhost by e28smtp04.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 24 Nov 2016 11:23:55 +0530 From: Nikunj A Dadhania In-Reply-To: <20161124010212.GK17795@umbus.fritz.box> References: <1479901039-7113-1-git-send-email-nikunj@linux.vnet.ibm.com> <1479901039-7113-10-git-send-email-nikunj@linux.vnet.ibm.com> <20161124010212.GK17795@umbus.fritz.box> Date: Thu, 24 Nov 2016 11:23:41 +0530 MIME-Version: 1.0 Content-Type: text/plain Message-Id: <878ts9xw2i.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> Subject: Re: [Qemu-devel] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com, Avinesh Kumar David Gibson writes: > [ Unknown signature status ] > On Wed, Nov 23, 2016 at 05:07:18PM +0530, Nikunj A Dadhania wrote: >> From: Avinesh Kumar >> >> vextublx: Vector Extract Unsigned Byte Left >> vextuhlx: Vector Extract Unsigned Halfword Left >> vextuwlx: Vector Extract Unsigned Word Left >> >> Signed-off-by: Avinesh Kumar >> Signed-off-by: Nikunj A Dadhania > > So, when I suggested doing these without helpers before, I had > forgotten that the non-byte versions can straddle the word boundary. > Given that the offset is in a register, not the instruction that does > make it complicated. > > But, this version also relies on working 128-bit arithmetic, AFAICT > this will just fail to build if CONFIG_INT128 isn't defined. It has both the implementation, just that the defines might have confused you: #if defined(HOST_WORDS_BIGENDIAN) # if defined(CONFIG_INT128) # else # endif #else /* !defined (HOST_WORDS_BIGENDIAN) */ # if defined(CONFIG_INT128) # else # endif #endif > It really shouldn't be that hard to make a helper that works just in > terms of 64-bit arithmetic - there are only 3 cases (all in the upper > word, all in the lower, and straddling). Currently, its being done using byte array. +{ \ + target_ulong r = 0; \ + int i; \ + int index = a & 0xf; \ + for (i = 0; i < elem; i++) { \ + r = r << 8; \ + if (index + i <= 15) { \ + r = r | b->u8[index + i]; \ + } \ + } \ + return r; \ +} > I'd prefer to see it done that way, rather than increasing reliance on > CONFIG_INT128. Regards Nikunj