From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38552) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UxhTt-0000WG-ET for qemu-devel@nongnu.org; Fri, 12 Jul 2013 13:50:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UxhTp-0003Yx-SN for qemu-devel@nongnu.org; Fri, 12 Jul 2013 13:50:09 -0400 Received: from mail-oa0-f43.google.com ([209.85.219.43]:39921) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UxhTp-0003YB-Nx for qemu-devel@nongnu.org; Fri, 12 Jul 2013 13:50:05 -0400 Received: by mail-oa0-f43.google.com with SMTP id i7so13122162oag.2 for ; Fri, 12 Jul 2013 10:50:05 -0700 (PDT) From: Anthony Liguori In-Reply-To: <1373628932.19894.158.camel@pasglop> References: <51C75FA6.6080903@reactos.org> <51C7E21A.9090005@web.de> <8A36D64D-0625-49E1-9E59-391DAEEBD1FC@suse.de> <51DEA91B.40903@suse.de> <3FAA7DE1-06A0-45C5-885C-0433BCC0CFE8@suse.de> <5D205309-1154-4730-902E-BF07F5D3B4EB@suse.de> <1373581960.19894.109.camel@pasglop> <02433CA4-954D-4C56-A4A4-7BC0D62638C0@suse.de> <1373628932.19894.158.camel@pasglop> Date: Fri, 12 Jul 2013 12:49:59 -0500 Message-ID: <878v1bvfaw.fsf@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt , Alexander Graf Cc: Liu Ping Fan , Jan Kiszka , qemu-devel Developers , "qemu-ppc@nongnu.org list:PowerPC" , Paolo Bonzini , Andreas =?utf-8?Q?F=C3=A4rber?= , =?utf-8?Q?Herv=C3=A9?= Poussineau Benjamin Herrenschmidt writes: > On Fri, 2013-07-12 at 05:18 +0200, Alexander Graf wrote: >> We model a single system wide io space today and access to that one >> happens through you pci host controller. I just messed up the >> terminology here. > > Single system wide IO space is broken. We have separate IO space per > PHB. That was working afaik. Hrm, probably not. We don't propagate I/O spaces very well today. > In any case, I completely object to all that business with conversion in > bridges. > > That's fundamentally WRONG. > > The whole business of endianness in qemu is a mess. In the end what > matters and the only thing that does is: It's not as bad as you think I suspect. > * The endianness of a given memory access by the guest (which may or > may not be the endianness of the guest -> MSR:LE, byteswap load/store > instsructions, etc..) Correct. > vs. > > * The endianness of the target device register (and I say register ... > a framebuffer does NOT have endianness per-se and thus accesses to BAR > mapping a "memory" range (framebuffer, ROM, ...) should go such that the > *byte order* of individual bytes is preserved, which typically means > untranslated). Yes. To put it another way, an MMIO write is a store and depending on the VCPU, that will result in a write with a certain byte order. That byte order should be preserved. However, what we don't model today, and why we have the silly endianness in MemoryRegionOps, is the fact that I/O may pass through multiple layers and those layers may change byte ordering. We jump through great hoops to have a flat dispatch table. I've never liked it but that's what we do. That means that in cases where a host bridge may do byte swapping, we cannot easily support that. That's really what endianness is for but it's abused. > Unless they are completely broken (and those exist, don't get me wrong, > though mostly they are a thing of a past long gone), bridges and busses > have no effect on endianness. That's simply not true. There are programmable PCI host bridges that support byte swapping. Some allow this to be done on a per-device basis too. > So I'm not sure what you guys are up to, but from what I read, it's > wrong, and the fact at this stage is that your broke IO space (and thus > virtio and VGA) on powerpc (including pseries). I'm not sure what this patch was trying to do but it was certainly wrong. Regards, Anthony Liguori > > Cheers, > Ben.