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Tue, 24 Jan 2023 10:47:46 +0000 (GMT) References: <20230106194451.1213153-1-richard.henderson@linaro.org> <20230106194451.1213153-3-richard.henderson@linaro.org> <3443cf40-4013-6ac6-895d-08f86c229809@linaro.org> User-agent: mu4e 1.9.16; emacs 29.0.60 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: Peter Maydell , qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: Re: [PATCH 2/2] target/arm: Look up ARMCPRegInfo at runtime Date: Tue, 24 Jan 2023 10:39:31 +0000 In-reply-to: <3443cf40-4013-6ac6-895d-08f86c229809@linaro.org> Message-ID: <87a628ryy5.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Richard Henderson writes: > On 1/23/23 02:53, Peter Maydell wrote: >> On Fri, 6 Jan 2023 at 19:45, Richard Henderson >> wrote: >>> >>> Do not encode the pointer as a constant in the opcode stream. >>> This pointer is specific to the cpu that first generated the >>> translation, which runs into problems with both hot-pluggable >>> cpus and user-only threads, as cpus are removed. >>> >>> Perform the lookup in either helper_access_check_cp_reg, >>> or a new helper_lookup_cp_reg. >> As well as the use-after-free, this is also a correctness >> bug, isn't it? If we hardwire in the cpregs pointer for >> CPU 0 into the TB, and then CPU 1 with a slightly different >> config executes the TB, it will get the cpregs of CPU 0, >> not its own, so it might see a register it should not or >> vice-versa. > > Existing assumption was that each cpu configuration would have its own > cluster_index, which gets encoded into cpu->tcg_cflags, which is part > of the comparison used when hashing TBs. I understand the cluster_index is used for things like A/R and A/M splits (and eventually heterogeneous). We also have language to cover the increasingly weird set of big.LITTLE offspring like M1's Performance/Efficiency split or the Tensor's X1/A76/A55 split. * If CPUs are not identical (for example, Cortex-A53 and Cortex-A57 CPUs i= n an * Arm big.LITTLE system) they should be in different clusters. If the CPUs= do * not have the same view of memory (for example the main CPU and a managem= ent * controller processor) they should be in different clusters. > But including this patch allows relaxation of what constitutes a "cpu con= figuration". > > > r~ --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro