From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF14CC43334 for ; Mon, 27 Jun 2022 10:11:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233424AbiF0KLc (ORCPT ); Mon, 27 Jun 2022 06:11:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231776AbiF0KL2 (ORCPT ); Mon, 27 Jun 2022 06:11:28 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FDDF6401; Mon, 27 Jun 2022 03:11:27 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id BF161B8106E; Mon, 27 Jun 2022 10:11:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 66AF1C3411D; Mon, 27 Jun 2022 10:11:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656324684; bh=uM9Jg0xWGjqPi0Q4iaOPjmzP/20updvm1fUGxrOmNGM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=G0lRwuQ5A6e7SuAtuHgJhvkJ9nOwh4bP0BSZ2uoYhzGNN347xKLZ79PT5l8WJS9Fg la8tZGg6YkAYUreLjih3n5IgGhpBnNyTBCaHlHkyky1F9M1t/CdfpKqVv+3KwCOd4O 0isOnQEIG3vwdUGH2JP26UKlfCyGJ/xeslFDLpXBYKGA/pYeQIr5EhKXL9T04l+ZgW h+RMJ/Q+2e5qD3xI62wre8v3GzN9Vp3jf54EfdTxKeTP32Ee2H5dM1MdnxscqM1V9w dSb54w2w8hFtwfi5NfH+n7NuVkQXK2gH0Fj8kV2HpzRF5QIkmslMz/+vNhbsm542aw DCCoNxhorI2fw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o5liE-003OOJ-5W; Mon, 27 Jun 2022 11:11:22 +0100 Date: Mon, 27 Jun 2022 11:11:21 +0100 Message-ID: <87a69y2z7a.wl-maz@kernel.org> From: Marc Zyngier To: Geert Uytterhoeven Cc: "Lad, Prabhakar" , Lad Prabhakar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Sagar Kadam , Palmer Dabbelt , Paul Walmsley , linux-riscv , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Geert Uytterhoeven , Linux-Renesas , LKML , Biju Das Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC In-Reply-To: References: <20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220626004326.8548-3-prabhakar.mahadev-lad.rj@bp.renesas.com> <87wnd3erab.wl-maz@kernel.org> <87v8snehwi.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: geert@linux-m68k.org, prabhakar.csengg@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sagar.kadam@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, geert+renesas@glider.be, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, biju.das.jz@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 27 Jun 2022 09:53:13 +0100, Geert Uytterhoeven wrote: > > Hi Marc, > > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier wrote: > > On Sun, 26 Jun 2022 10:38:18 +0100, > > "Lad, Prabhakar" wrote: > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier wrote: > > > > On Sun, 26 Jun 2022 01:43:26 +0100, > > > > Lad Prabhakar wrote: > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt > > > > > edge until the previous completion message has been received and > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the > > > > > interrupts if not acknowledged in time. > > > > > > > > > > So the workaround for edge-triggered interrupts to be handled correctly > > > > > and without losing is that it needs to be acknowledged first and then > > > > > handler must be run so that we don't miss on the next edge-triggered > > > > > interrupt. > > > > > > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds > > > > > support to change interrupt flow based on the interrupt type. It also > > > > > implements irq_ack and irq_set_type callbacks. > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > + if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) { > > > > > + priv->of_data = RENESAS_R9A07G043_PLIC; > > > > > + plic_chip.name = "Renesas RZ/Five PLIC"; > > > > > > > > NAK. The irq_chip structure isn't the place for platform marketing. > > > > This is way too long anyway (and same for the edge version), and you > > > > even sent me a patch to make that structure const... > > > > > > > My bad will drop this. > > > > And why you're at it, please turn this rather random 'of_data' into > > something like: > > > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > > index bb87e4c3b88e..cd1683b77caf 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -64,6 +64,10 @@ struct plic_priv { > > struct cpumask lmask; > > struct irq_domain *irqdomain; > > void __iomem *regs; > > + enum { > > + VANILLA_PLIC, > > + RENESAS_R9A07G043_PLIC, > > + } flavour; > > }; > > > > struct plic_handler { > > > > to give some structure to the whole thing, because I'm pretty sure > > we'll see more braindead implementations as time goes by. > > What about using a feature flag (e.g. had_edge_irqs) instead? Sure. Then make this an unsigned long, and have a set of quirk bits, because I expect this to grow quickly. > > > It almost feels like I've written this whole patch. Oh wait... > > > Without deviation from the norm, progress is not possible. > > How applicable ;-) I'm not sure there is any sign of progress here, and evolution through random mutation has a pretty massive failure rate. Thanks, M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 203E2C43334 for ; Mon, 27 Jun 2022 10:11:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=q1nXxkzoDecC4MH7rp7GtYI0RoPFmWU1sQ3ihb9gIf0=; b=MXypk6ViZaQ+7Q EqCDeLtKkudbZ9Eq6nlIuYojZzx/M8ylC2ivxzjP4hUQKcidIBGq4Dre81dqwKfe9z86e0T1+wHTD gFeXBCrL7tz3mz2QxUHlnhedwdveglh0T09ndqZkZOaR8ZW/8ioiuUflbQucvlzhNOvKa7DZgO6IC 1lav2J4HGdQGID0iTjZt7/+nOnCv7OwkvnAQR82SbdSO3nZAxne8PBHLfJe3z2jr0pSOi4Ue34yl7 R9tA8TJ565Ew4U/vMhQT6uptiNWNkwlW3mAO3lzRIlIYEZKHtJ+fSnSZNPYH2oqfZaR7d/AO8e644 rP17C7p9/EfXcFwJ3tgA==; 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Mon, 27 Jun 2022 11:11:22 +0100 Date: Mon, 27 Jun 2022 11:11:21 +0100 Message-ID: <87a69y2z7a.wl-maz@kernel.org> From: Marc Zyngier To: Geert Uytterhoeven Cc: "Lad, Prabhakar" , Lad Prabhakar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Sagar Kadam , Palmer Dabbelt , Paul Walmsley , linux-riscv , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Geert Uytterhoeven , Linux-Renesas , LKML , Biju Das Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC In-Reply-To: References: <20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220626004326.8548-3-prabhakar.mahadev-lad.rj@bp.renesas.com> <87wnd3erab.wl-maz@kernel.org> <87v8snehwi.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: geert@linux-m68k.org, prabhakar.csengg@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sagar.kadam@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, geert+renesas@glider.be, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, biju.das.jz@bp.renesas.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220627_031127_157899_5C58F9D3 X-CRM114-Status: GOOD ( 41.78 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, 27 Jun 2022 09:53:13 +0100, Geert Uytterhoeven wrote: > > Hi Marc, > > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier wrote: > > On Sun, 26 Jun 2022 10:38:18 +0100, > > "Lad, Prabhakar" wrote: > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier wrote: > > > > On Sun, 26 Jun 2022 01:43:26 +0100, > > > > Lad Prabhakar wrote: > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt > > > > > edge until the previous completion message has been received and > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the > > > > > interrupts if not acknowledged in time. > > > > > > > > > > So the workaround for edge-triggered interrupts to be handled correctly > > > > > and without losing is that it needs to be acknowledged first and then > > > > > handler must be run so that we don't miss on the next edge-triggered > > > > > interrupt. > > > > > > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds > > > > > support to change interrupt flow based on the interrupt type. It also > > > > > implements irq_ack and irq_set_type callbacks. > > > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > + if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) { > > > > > + priv->of_data = RENESAS_R9A07G043_PLIC; > > > > > + plic_chip.name = "Renesas RZ/Five PLIC"; > > > > > > > > NAK. The irq_chip structure isn't the place for platform marketing. > > > > This is way too long anyway (and same for the edge version), and you > > > > even sent me a patch to make that structure const... > > > > > > > My bad will drop this. > > > > And why you're at it, please turn this rather random 'of_data' into > > something like: > > > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c > > index bb87e4c3b88e..cd1683b77caf 100644 > > --- a/drivers/irqchip/irq-sifive-plic.c > > +++ b/drivers/irqchip/irq-sifive-plic.c > > @@ -64,6 +64,10 @@ struct plic_priv { > > struct cpumask lmask; > > struct irq_domain *irqdomain; > > void __iomem *regs; > > + enum { > > + VANILLA_PLIC, > > + RENESAS_R9A07G043_PLIC, > > + } flavour; > > }; > > > > struct plic_handler { > > > > to give some structure to the whole thing, because I'm pretty sure > > we'll see more braindead implementations as time goes by. > > What about using a feature flag (e.g. had_edge_irqs) instead? Sure. Then make this an unsigned long, and have a set of quirk bits, because I expect this to grow quickly. > > > It almost feels like I've written this whole patch. Oh wait... > > > Without deviation from the norm, progress is not possible. > > How applicable ;-) I'm not sure there is any sign of progress here, and evolution through random mutation has a pretty massive failure rate. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv