From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35F5BC433F5 for ; Mon, 25 Oct 2021 10:48:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19DD560FDC for ; Mon, 25 Oct 2021 10:48:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230481AbhJYKvB (ORCPT ); Mon, 25 Oct 2021 06:51:01 -0400 Received: from mail.kernel.org ([198.145.29.99]:38140 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230111AbhJYKu6 (ORCPT ); Mon, 25 Oct 2021 06:50:58 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3C65560FDC; Mon, 25 Oct 2021 10:48:36 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mexWr-001L6M-VV; Mon, 25 Oct 2021 11:48:34 +0100 Date: Mon, 25 Oct 2021 11:48:33 +0100 Message-ID: <87a6ixbcse.wl-maz@kernel.org> From: Marc Zyngier To: guoren@kernel.org Cc: anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead,c900-plic request_threaded_irq with ONESHOT In-Reply-To: <20211024013303.3499461-4-guoren@kernel.org> References: <20211024013303.3499461-1-guoren@kernel.org> <20211024013303.3499461-4-guoren@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, guoren@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 24 Oct 2021 02:33:03 +0100, guoren@kernel.org wrote: > > From: Guo Ren > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the driver, > only the first interrupt could be handled, and continue irq is blocked by > hw. Because the thead,c900-plic couldn't complete masked irq source which > has been disabled in enable register. Add thead_plic_chip which fix up > c906-plic irq source completion problem by unmask/mask wrapper. > > Here is the description of Interrupt Completion in PLIC spec [1]: > > The PLIC signals it has completed executing an interrupt handler by > writing the interrupt ID it received from the claim to the claim/complete > register. The PLIC does not check whether the completion ID is the same > as the last claim ID for that target. If the completion ID does not match > an interrupt source that is currently enabled for the target, the > ^^ ^^^^^^^^^ ^^^^^^^ > completion is silently ignored. Given this bit of the spec... > +static void plic_thead_irq_eoi(struct irq_data *d) > +{ > + struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > + > + if (irqd_irq_masked(d)) { > + plic_irq_unmask(d); > + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > + plic_irq_mask(d); > + } else { > + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > + } > +} > + ... it isn't obvious to me why this cannot happen on an SiFive PLIC. And it isn't only for threaded interrupts in oneshot mode. Any driver can mask an interrupt from its handler after having set the IRQ_DISABLE_UNLAZY flag, and the interrupt would need the exact same treatment. M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1565DC433F5 for ; Mon, 25 Oct 2021 10:48:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D11BC60FDC for ; Mon, 25 Oct 2021 10:48:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D11BC60FDC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kI6Vsb5sWy4u3aOW1Fz6iWdeh1tPfBqlMQ0wpVVCNjU=; b=HCb2bWGcrMYfr5 lbr+qfK85HeS2AukiIPXpKHWgd+ye0Ud8ocX9xiFTbtF/gnNQ1rzt0uHu7xmavRc4/+l3VYfATHx5 UN1N/jHURjNNYSCYoswIRWn9bHGeIYw3hwGhLHGRRsAKSNBM3RNodPxEVH3RCLH/bO4d0kmad1zc8 EeVr3DAXJycOrSt2rVKbj2bvAg0BOv+HyceFB9lwlKmayVJzCj4J8dahDAigjuCaRL2GAIDDHNboq Jlk/qodSCg7zlsmTv2RDLCa4s3Q0vNGJPmE4qHGtsMH9oLVFJp64NF1o1jmsU1cClA7LrVcUM0wAZ 6W70eVLlVcJTa9HshACQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mexWw-00G7Q1-OA; Mon, 25 Oct 2021 10:48:38 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mexWu-00G7P0-Hn for linux-riscv@lists.infradead.org; Mon, 25 Oct 2021 10:48:37 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3C65560FDC; Mon, 25 Oct 2021 10:48:36 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mexWr-001L6M-VV; Mon, 25 Oct 2021 11:48:34 +0100 Date: Mon, 25 Oct 2021 11:48:33 +0100 Message-ID: <87a6ixbcse.wl-maz@kernel.org> From: Marc Zyngier To: guoren@kernel.org Cc: anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT In-Reply-To: <20211024013303.3499461-4-guoren@kernel.org> References: <20211024013303.3499461-1-guoren@kernel.org> <20211024013303.3499461-4-guoren@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com, tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de, robh@kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, guoren@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211025_034836_655020_4B154A75 X-CRM114-Status: GOOD ( 23.70 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, 24 Oct 2021 02:33:03 +0100, guoren@kernel.org wrote: > > From: Guo Ren > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the driver, > only the first interrupt could be handled, and continue irq is blocked by > hw. Because the thead,c900-plic couldn't complete masked irq source which > has been disabled in enable register. Add thead_plic_chip which fix up > c906-plic irq source completion problem by unmask/mask wrapper. > > Here is the description of Interrupt Completion in PLIC spec [1]: > > The PLIC signals it has completed executing an interrupt handler by > writing the interrupt ID it received from the claim to the claim/complete > register. The PLIC does not check whether the completion ID is the same > as the last claim ID for that target. If the completion ID does not match > an interrupt source that is currently enabled for the target, the > ^^ ^^^^^^^^^ ^^^^^^^ > completion is silently ignored. Given this bit of the spec... > +static void plic_thead_irq_eoi(struct irq_data *d) > +{ > + struct plic_handler *handler = this_cpu_ptr(&plic_handlers); > + > + if (irqd_irq_masked(d)) { > + plic_irq_unmask(d); > + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > + plic_irq_mask(d); > + } else { > + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); > + } > +} > + ... it isn't obvious to me why this cannot happen on an SiFive PLIC. And it isn't only for threaded interrupts in oneshot mode. Any driver can mask an interrupt from its handler after having set the IRQ_DISABLE_UNLAZY flag, and the interrupt would need the exact same treatment. M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv