From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 218D0C433DB for ; Wed, 10 Mar 2021 09:42:07 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8AEE164F70 for ; Wed, 10 Mar 2021 09:42:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8AEE164F70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Subject:Cc:To: From:Message-ID:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BBEP0fdQrsoS7dwH0RUQPG1Dql0bssasit578RmjViU=; b=aPqk/n/2yTdSx669/gaw6AwLu vhw8bwaYn5VdFOH9SMg3FooJvRTVoiejM3JZFentOm+hccMWa1eqLW/24eXuvdzPq5+E6ZjK2LoLw kozbNWD6B/YDsdAf2alZC0JvPVNVjxp3xxmVpklLs/zEfltd20JsAZm1qIRfrXH7N2b6D4srdr82d Ul32Dgmx34mYCBShuHBxMPyyS1dCmyOSOWP6J84MSPFM/nDCe3eIt750Ri4pigbClLoyNBTuRgVYi VAn4c0VKDlKmvW9u9aytdrjaHrL2De4DbRAaqqj8p9IRV2iXdbn6bSUx/A0Ue7iImcF+YikUh+gfv dt0qVCcbw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lJvLm-006TmH-08; Wed, 10 Mar 2021 09:41:54 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lJvLY-006TlL-Ei; Wed, 10 Mar 2021 09:41:44 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id AF23D64F70; Wed, 10 Mar 2021 09:41:38 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lJvLU-000j0K-BD; Wed, 10 Mar 2021 09:41:36 +0000 Date: Wed, 10 Mar 2021 09:41:35 +0000 Message-ID: <87a6rbxs4w.wl-maz@kernel.org> From: Marc Zyngier To: Jianjun Wang Cc: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Ryder Lee , Philipp Zabel , "Matthias\ Brugger" , , , , , , "Sj\ Huang" , , , , , , , Subject: Re: [v8,5/7] PCI: mediatek-gen3: Add MSI support In-Reply-To: <1615358929.25662.47.camel@mhfsdcap03> References: <20210224061132.26526-1-jianjun.wang@mediatek.com> <20210224061132.26526-6-jianjun.wang@mediatek.com> <87pn08y3ja.wl-maz@kernel.org> <1615358929.25662.47.camel@mhfsdcap03> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: jianjun.wang@mediatek.com, bhelgaas@google.com, robh+dt@kernel.org, lorenzo.pieralisi@arm.com, ryder.lee@mediatek.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sj.huang@mediatek.com, youlin.pei@mediatek.com, chuanjia.liu@mediatek.com, qizhong.cheng@mediatek.com, sin_jieyang@mediatek.com, drinkcat@chromium.org, Rex-BC.Chen@mediatek.com, anson.chuang@mediatek.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210310_094143_015732_BC4ED300 X-CRM114-Status: GOOD ( 36.24 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Wed, 10 Mar 2021 06:48:49 +0000, Jianjun Wang wrote: > > > +static struct irq_chip mtk_msi_irq_chip = { > > > + .name = "MSI", > > > + .irq_enable = mtk_pcie_irq_unmask, > > > + .irq_disable = mtk_pcie_irq_mask, > > > > Same comment as for the previous patch: enable/disable serve no > > purpose here. > > Replied in the previous patch, the enable/disable callback is used when > the system suspend/resume. As I said, your suspend/resume should be self contained, and not rely on the irq subsystem to restore a viable state. [...] > > > @@ -408,6 +677,14 @@ static void mtk_pcie_irq_handler(struct irq_desc *desc) > > > generic_handle_irq(virq); > > > } > > > > > > + irq_bit = PCIE_MSI_SHIFT; > > > + for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM + > > > + PCIE_MSI_SHIFT) { > > > + mtk_pcie_msi_handler(port, irq_bit - PCIE_MSI_SHIFT); > > > + > > > + writel_relaxed(BIT(irq_bit), port->base + PCIE_INT_STATUS_REG); > > > > Isn't this write the same thing you have for EOI in the INTx case? > > While I could understand your description in that case (this is a > > resampling operation), I don't get what this does here. Either this is > > also an EOI, but your initial description doesn't make sense, or it is > > an Ack, and it should be moved to the right place. > > > > Which one is it? > > I think it should be an EOI which used to clear the interrupt status of > a single set in the PCIe intc field, maybe I should move it to the end > of the mtk_pcie_msi_handler() function. I doubt this is an EOI. If, as I suspect, it instructs the HW to clear the bit so that new pending bits can be recorded, it must take place *before* the interrupt is handled, or you may lose MSIs in the interval between the handling of the interrupt and the clearing of the pending bit. To satisfy this requirement, this should be an ACK, which is consistent with the way most MSI controllers such as this one work. > > +-----+ > | GIC | > +-----+ > ^ > | > port->irq > | > +-+-+-+-+-+-+-+-+ > |0|1|2|3|4|5|6|7| (PCIe intc) > +-+-+-+-+-+-+-+-+ > ^ ^ ^ > | | ... | > +-------+ +------+ +-----------+ > | | | > +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ > |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) > +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ > ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ > | | | | | | | | | | | | (MSI vectors) > | | | | | | | | | | | | > > (MSI SET0) (MSI SET1) ... (MSI SET7) > > I would like to ask another question. In this interrupt architecture, we > cannot implement an affinity for PCIe interrupts, so we return a > negative value in the mtk_pcie_set_affinity callback as follows: > > +static int mtk_pcie_set_affinity(struct irq_data *data, > + const struct cpumask *mask, bool force) > +{ > + return -EINVAL; > +} > > But there will always be error logs when hotplug a CPU: > > ~ # echo 0 > /sys/devices/system/cpu/cpu1/online > [ 93.633059] IRQ255: set affinity failed(-22). > [ 93.633624] IRQ256: set affinity failed(-22). > [ 93.634222] CPU1: shutdown > [ 93.634586] psci: CPU1 killed (polled 0 ms) > > Or when the system suspends: > > ~ # echo mem > /sys/power/state > [ 93.635145] cpuhp: cpu_off cluster=0, cpu=1 > [ 169.835653] PM: suspend entry (deep) > [ 169.836717] Filesystems sync: 0.000 seconds > [ 169.837924] Freezing user space processes ... (elapsed 0.001 seconds) > done. > [ 169.839922] OOM killer disabled. > [ 169.840336] Freezing remaining freezable tasks ... (elapsed 0.001 > seconds) done. > [ 169.844715] Disabling non-boot CPUs ... > [ 169.846443] IRQ255: set affinity failed(-22). > [ 169.847002] IRQ256: set affinity failed(-22). > [ 169.847586] CPU2: shutdown > [ 169.847943] psci: CPU2 killed (polled 0 ms) > [ 169.848489] cpuhp: cpu_off cluster=0, cpu=2 > [ 169.850285] IRQ255: set affinity failed(-22). > [ 169.851369] IRQ256: set affinity failed(-22). > ... > > Sometimes this can cause misunderstandings to users, do we have a chance > to prevent this error log? No. This HW doesn't allow MSIs to be individually retargeted, and the kernel isn't happy about that. That's one of the many reasons why hiding MSIs behind a mux (or two in your case) is a *very bad idea*. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEB1BC433DB for ; Wed, 10 Mar 2021 09:43:18 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B1BD64F70 for ; Wed, 10 Mar 2021 09:43:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1B1BD64F70 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Subject:Cc:To: From:Message-ID:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=h8bGSMoLyzRsoW8xLVWlGB1/w901PyUKaGM2I26Lxjk=; b=RbA+jlRXd4hhqU0aT7wd7IVe5 iNg50hagwKWl8dMMoqumMoabA/h9G2B8Ga2qAPzeW9cdPY+zkdA89/Wny1Fzp7Rq+jdYCsn9LZGVM hXITSb7Z4u2cOd8Nm7MlUP9xcYFOaqp6Hxqgk7tHWvItHamNYIYk0anvtrxLc5JsX8PvTM/uYJ1/J X8RpLDKqtWw8KHYrzanBfD4yuQx1T05t5fEMR7LV676NVDqZ2yWmslCqfL+1n8WlZM1oVtiz6KwRW Oc/6zexk4HxL7IyShLGFekbaL865Bj8WVNcnDIV/McvVCmw1FcDrp5GOlFX0aUk3dO5PJq4VSI+Zr zLLyaQ7Ig==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lJvLf-006Tlu-FL; Wed, 10 Mar 2021 09:41:47 +0000 Received: from mail.kernel.org ([198.145.29.99]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lJvLY-006TlL-Ei; Wed, 10 Mar 2021 09:41:44 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id AF23D64F70; Wed, 10 Mar 2021 09:41:38 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lJvLU-000j0K-BD; Wed, 10 Mar 2021 09:41:36 +0000 Date: Wed, 10 Mar 2021 09:41:35 +0000 Message-ID: <87a6rbxs4w.wl-maz@kernel.org> From: Marc Zyngier To: Jianjun Wang Cc: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Ryder Lee , Philipp Zabel , "Matthias\ Brugger" , , , , , , "Sj\ Huang" , , , , , , , Subject: Re: [v8,5/7] PCI: mediatek-gen3: Add MSI support In-Reply-To: <1615358929.25662.47.camel@mhfsdcap03> References: <20210224061132.26526-1-jianjun.wang@mediatek.com> <20210224061132.26526-6-jianjun.wang@mediatek.com> <87pn08y3ja.wl-maz@kernel.org> <1615358929.25662.47.camel@mhfsdcap03> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: jianjun.wang@mediatek.com, bhelgaas@google.com, robh+dt@kernel.org, lorenzo.pieralisi@arm.com, ryder.lee@mediatek.com, p.zabel@pengutronix.de, matthias.bgg@gmail.com, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sj.huang@mediatek.com, youlin.pei@mediatek.com, chuanjia.liu@mediatek.com, qizhong.cheng@mediatek.com, sin_jieyang@mediatek.com, drinkcat@chromium.org, Rex-BC.Chen@mediatek.com, anson.chuang@mediatek.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210310_094143_015732_BC4ED300 X-CRM114-Status: GOOD ( 36.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 10 Mar 2021 06:48:49 +0000, Jianjun Wang wrote: > > > +static struct irq_chip mtk_msi_irq_chip = { > > > + .name = "MSI", > > > + .irq_enable = mtk_pcie_irq_unmask, > > > + .irq_disable = mtk_pcie_irq_mask, > > > > Same comment as for the previous patch: enable/disable serve no > > purpose here. > > Replied in the previous patch, the enable/disable callback is used when > the system suspend/resume. As I said, your suspend/resume should be self contained, and not rely on the irq subsystem to restore a viable state. [...] > > > @@ -408,6 +677,14 @@ static void mtk_pcie_irq_handler(struct irq_desc *desc) > > > generic_handle_irq(virq); > > > } > > > > > > + irq_bit = PCIE_MSI_SHIFT; > > > + for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM + > > > + PCIE_MSI_SHIFT) { > > > + mtk_pcie_msi_handler(port, irq_bit - PCIE_MSI_SHIFT); > > > + > > > + writel_relaxed(BIT(irq_bit), port->base + PCIE_INT_STATUS_REG); > > > > Isn't this write the same thing you have for EOI in the INTx case? > > While I could understand your description in that case (this is a > > resampling operation), I don't get what this does here. Either this is > > also an EOI, but your initial description doesn't make sense, or it is > > an Ack, and it should be moved to the right place. > > > > Which one is it? > > I think it should be an EOI which used to clear the interrupt status of > a single set in the PCIe intc field, maybe I should move it to the end > of the mtk_pcie_msi_handler() function. I doubt this is an EOI. If, as I suspect, it instructs the HW to clear the bit so that new pending bits can be recorded, it must take place *before* the interrupt is handled, or you may lose MSIs in the interval between the handling of the interrupt and the clearing of the pending bit. To satisfy this requirement, this should be an ACK, which is consistent with the way most MSI controllers such as this one work. > > +-----+ > | GIC | > +-----+ > ^ > | > port->irq > | > +-+-+-+-+-+-+-+-+ > |0|1|2|3|4|5|6|7| (PCIe intc) > +-+-+-+-+-+-+-+-+ > ^ ^ ^ > | | ... | > +-------+ +------+ +-----------+ > | | | > +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ > |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) > +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ > ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ > | | | | | | | | | | | | (MSI vectors) > | | | | | | | | | | | | > > (MSI SET0) (MSI SET1) ... (MSI SET7) > > I would like to ask another question. In this interrupt architecture, we > cannot implement an affinity for PCIe interrupts, so we return a > negative value in the mtk_pcie_set_affinity callback as follows: > > +static int mtk_pcie_set_affinity(struct irq_data *data, > + const struct cpumask *mask, bool force) > +{ > + return -EINVAL; > +} > > But there will always be error logs when hotplug a CPU: > > ~ # echo 0 > /sys/devices/system/cpu/cpu1/online > [ 93.633059] IRQ255: set affinity failed(-22). > [ 93.633624] IRQ256: set affinity failed(-22). > [ 93.634222] CPU1: shutdown > [ 93.634586] psci: CPU1 killed (polled 0 ms) > > Or when the system suspends: > > ~ # echo mem > /sys/power/state > [ 93.635145] cpuhp: cpu_off cluster=0, cpu=1 > [ 169.835653] PM: suspend entry (deep) > [ 169.836717] Filesystems sync: 0.000 seconds > [ 169.837924] Freezing user space processes ... (elapsed 0.001 seconds) > done. > [ 169.839922] OOM killer disabled. > [ 169.840336] Freezing remaining freezable tasks ... (elapsed 0.001 > seconds) done. > [ 169.844715] Disabling non-boot CPUs ... > [ 169.846443] IRQ255: set affinity failed(-22). > [ 169.847002] IRQ256: set affinity failed(-22). > [ 169.847586] CPU2: shutdown > [ 169.847943] psci: CPU2 killed (polled 0 ms) > [ 169.848489] cpuhp: cpu_off cluster=0, cpu=2 > [ 169.850285] IRQ255: set affinity failed(-22). > [ 169.851369] IRQ256: set affinity failed(-22). > ... > > Sometimes this can cause misunderstandings to users, do we have a chance > to prevent this error log? No. This HW doesn't allow MSIs to be individually retargeted, and the kernel isn't happy about that. That's one of the many reasons why hiding MSIs behind a mux (or two in your case) is a *very bad idea*. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel