* [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES
@ 2017-02-07 12:43 Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
` (8 more replies)
0 siblings, 9 replies; 16+ messages in thread
From: Madhav Chauhan @ 2017-02-07 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula
The patches in this list enable MIPI DSI video mode
support for GLK platform. Tesed locally.
v2: Renamed bitfields macros as per review comments(Jani)
v3: Code alignment/abstraction as per arch (Jani review comments)
v4: Fix DSI disable sequence, pll divider checks. Review comments(Jani)
Deepak M (7):
drm/i915/glk: Program dphy param reg for GLK
drm/i915/glk: Program new MIPI DSI PHY registers for GLK
drm/i915/glk: Add MIPIIO Enable/disable sequence
drm/i915: Set the Z inversion overlap field
drm/i915/glk: Add DSI PLL divider range for glk
drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
drm/i915/glk: Program txesc clock divider for GLK
Madhav Chauhan (1):
drm/i915/glk: Validate only DSI PORT A PLL divider
drivers/gpu/drm/i915/i915_reg.h | 17 +++
drivers/gpu/drm/i915/intel_dsi.c | 230 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 45 ++++--
drivers/gpu/drm/i915/intel_dsi_pll.c | 125 +++++++++++++---
4 files changed, 364 insertions(+), 53 deletions(-)
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
@ 2017-02-07 12:43 ` Madhav Chauhan
2017-02-08 14:53 ` Jani Nikula
2017-02-07 12:43 ` [GLK MIPI DSI V4 2/8] drm/i915/glk: Program new MIPI DSI PHY registers " Madhav Chauhan
` (7 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Madhav Chauhan @ 2017-02-07 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula, Deepak M
From: Deepak M <m.deepak@intel.com>
For GEMINILAKE, dphy param reg values are programmed in terms
of HS byte clock count while for older platforms in terms of
HS ddr clk count.
v2: Added comments to clarify ddr clock count calculation
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 45 ++++++++++++++++++++----------
1 file changed, 31 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 8f683b8..b3c495f 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -674,11 +674,6 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
break;
}
- /*
- * ui(s) = 1/f [f in hz]
- * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
- */
-
/* in Kbps */
ui_num = NS_KHZ_RATIO;
ui_den = bitrate;
@@ -692,19 +687,32 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
*/
intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
- /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
+ /* DDR clock period = 2 * UI
+ * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
+ * UI(nsec) = 10^6 / bitrate
+ * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
+ * DDR clock count = ns_value / DDR clock period
*
- * Since txddrclkhs_i is 2xUI, all the count values programmed in
- * DPHY param register are divided by 2
+ * For GEMINILAKE dphy_param_reg will be programmed in terms of
+ * HS byte clock count for other platform in HS ddr clock count
*
* prepare count
*/
ths_prepare_ns = max(mipi_config->ths_prepare,
mipi_config->tclk_prepare);
- prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
+ if (IS_GEMINILAKE(dev_priv))
+ prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 8);
+ else
+ prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
/* exit zero count */
- exit_zero_cnt = DIV_ROUND_UP(
+ if (IS_GEMINILAKE(dev_priv))
+ exit_zero_cnt = DIV_ROUND_UP(
+ (ths_prepare_hszero - ths_prepare_ns) * ui_den,
+ ui_num * 8
+ );
+ else
+ exit_zero_cnt = DIV_ROUND_UP(
(ths_prepare_hszero - ths_prepare_ns) * ui_den,
ui_num * 2
);
@@ -719,13 +727,22 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
exit_zero_cnt += 1;
/* clk zero count */
- clk_zero_cnt = DIV_ROUND_UP(
- (tclk_prepare_clkzero - ths_prepare_ns)
- * ui_den, 2 * ui_num);
+ if (IS_GEMINILAKE(dev_priv))
+ clk_zero_cnt = DIV_ROUND_UP(
+ (tclk_prepare_clkzero - ths_prepare_ns)
+ * ui_den, 8 * ui_num);
+ else
+ clk_zero_cnt = DIV_ROUND_UP(
+ (tclk_prepare_clkzero - ths_prepare_ns)
+ * ui_den, 2 * ui_num);
/* trail count */
tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
- trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
+
+ if (IS_GEMINILAKE(dev_priv))
+ trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 * ui_num);
+ else
+ trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
if (prepare_cnt > PREPARE_CNT_MAX ||
exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [GLK MIPI DSI V4 2/8] drm/i915/glk: Program new MIPI DSI PHY registers for GLK
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
@ 2017-02-07 12:43 ` Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
` (6 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Madhav Chauhan @ 2017-02-07 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula, Deepak M
From: Deepak M <m.deepak@intel.com>
Program the clk lane and tlpx time count registers
to configure DSI PHY.
v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Program clk lane timing reg same as dphy param reg.
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
drivers/gpu/drm/i915/intel_dsi.c | 7 +++++++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31e9583..80ba02a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8603,6 +8603,14 @@ enum {
#define LP_BYTECLK_SHIFT 0
#define LP_BYTECLK_MASK (0xffff << 0)
+#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
+#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
+#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
+
+#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
+#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
+#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
+
/* bits 31:0 */
#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 16732e7..be81283 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1279,6 +1279,13 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
*/
I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
+ if (IS_GEMINILAKE(dev_priv)) {
+ I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
+ intel_dsi->lp_byte_clk);
+ /* Shadow of DPHY reg */
+ I915_WRITE(MIPI_CLK_LANE_TIMING(port), intel_dsi->dphy_reg);
+ }
+
/* the bw essential for transmitting 16 long packets containing
* 252 bytes meant for dcs write memory command is programmed in
* this register in terms of byte clocks. based on dsi transfer
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [GLK MIPI DSI V4 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 2/8] drm/i915/glk: Program new MIPI DSI PHY registers " Madhav Chauhan
@ 2017-02-07 12:43 ` Madhav Chauhan
2017-02-08 14:58 ` Jani Nikula
2017-02-07 12:43 ` [GLK MIPI DSI V4 4/8] drm/i915: Set the Z inversion overlap field Madhav Chauhan
` (5 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Madhav Chauhan @ 2017-02-07 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula, Deepak M
From: Deepak M <m.deepak@intel.com>
v2: Addressed Jani's Review comments(renamed bit field macros)
v3: Jani's Review comment for aligning code to platforms and added
wrapper functions.
v4: Corrected enable/disable seuqence as per BSPEC
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 206 ++++++++++++++++++++++++++++++++++++---
1 file changed, 195 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index be81283..0def214 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
return true;
}
+static void glk_dsi_device_ready(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 tmp, val;
+
+ /* Set the MIPI mode
+ * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
+ * Power ON MIPI IO first and then write into IO reset and LP wake bits
+ */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(MIPI_CTRL(port));
+ I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
+ }
+
+ /* Put the IO into reset */
+ tmp = I915_READ(MIPI_CTRL(PORT_A));
+ tmp &= ~GLK_MIPIIO_RESET_RELEASED;
+ I915_WRITE(MIPI_CTRL(PORT_A), tmp);
+
+ /* Program LP Wake */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(MIPI_CTRL(port));
+ tmp |= GLK_LP_WAKE;
+ I915_WRITE(MIPI_CTRL(port), tmp);
+ }
+
+ /* Wait for Pwr ACK */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
+ GLK_MIPIIO_PORT_POWERED, 20))
+ DRM_ERROR("Power ACK not received\n");
+ }
+
+ /* Wait for MIPI PHY status bit to set */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
+ GLK_MIPIIO_PORT_POWERED, 20))
+ DRM_ERROR("PHY is not ON\n");
+ }
+
+ /* Get IO out of reset */
+ tmp = I915_READ(MIPI_CTRL(PORT_A));
+ I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
+
+ /* Get IO out of Low power state*/
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= DEVICE_READY;
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+ usleep_range(10, 15);
+ }
+
+ /* Enter ULPS */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_ENTER | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+ /* Wait for ULPS Not active */
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
+ GLK_ULPS_NOT_ACTIVE, 20))
+
+ /* Exit ULPS */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_EXIT | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+ /* Enter Normal Mode */
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+
+ tmp = I915_READ(MIPI_CTRL(port));
+ tmp &= ~GLK_LP_WAKE;
+ I915_WRITE(MIPI_CTRL(port), tmp);
+ }
+
+ /* Wait for Stop state */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
+ GLK_DATA_LANE_STOP_STATE, 20))
+ DRM_ERROR("Date lane not in STOP state\n");
+ }
+
+ /* Wait for AFE LATCH */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
+ AFE_LATCHOUT, 20))
+ DRM_ERROR("D-PHY not entering LP-11 state\n");
+ }
+}
+
static void bxt_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -442,8 +545,10 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_device_ready(encoder);
- else if (IS_GEN9_LP(dev_priv))
+ else if (IS_BROXTON(dev_priv))
bxt_dsi_device_ready(encoder);
+ else if (IS_GEMINILAKE(dev_priv))
+ glk_dsi_device_ready(encoder);
}
static void intel_dsi_port_enable(struct intel_encoder *encoder)
@@ -637,18 +742,20 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
msleep(2);
}
- for_each_dsi_port(port, intel_dsi->ports) {
- /* Panel commands can be sent when clock is in LP11 */
- I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
+ if (!IS_GEMINILAKE(dev_priv)) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ /* Panel commands can be sent when clock is in LP11 */
+ I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
- intel_dsi_reset_clocks(encoder, port);
- I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
+ intel_dsi_reset_clocks(encoder, port);
+ I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
- temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
- temp &= ~VID_MODE_FORMAT_MASK;
- I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
+ temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
+ temp &= ~VID_MODE_FORMAT_MASK;
+ I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
- I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+ I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+ }
}
/* if disable packets are sent before sending shutdown packet then in
* some next enable sequence send turn on packet error is observed */
@@ -658,7 +765,73 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
wait_for_dsi_fifo_empty(intel_dsi, port);
}
-static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
+static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 val;
+
+ /* Enter ULPS */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ val = I915_READ(MIPI_DEVICE_READY(port));
+ val &= ~ULPS_STATE_MASK;
+ val |= (ULPS_STATE_ENTER | DEVICE_READY);
+ I915_WRITE(MIPI_DEVICE_READY(port), val);
+ }
+
+ /* Wait for MIPI PHY status bit to unset */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port),
+ GLK_PHY_STATUS_PORT_READY, 0, 20))
+ DRM_ERROR("PHY is not turning OFF\n");
+ }
+
+ /* Wait for Pwr ACK bit to unset */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port),
+ GLK_MIPIIO_PORT_POWERED, 0, 20))
+ DRM_ERROR("MIPI IO Port is not powergated\n");
+ }
+}
+
+static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum port port;
+ u32 tmp;
+
+ /* Put the IO into reset */
+ tmp = I915_READ(MIPI_CTRL(PORT_A));
+ tmp &= ~GLK_MIPIIO_RESET_RELEASED;
+ I915_WRITE(MIPI_CTRL(PORT_A), tmp);
+
+ /* Wait for MIPI PHY status bit to unset */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ if (intel_wait_for_register(dev_priv,
+ MIPI_CTRL(port),
+ GLK_PHY_STATUS_PORT_READY, 0, 20))
+ DRM_ERROR("PHY is not turning OFF\n");
+ }
+
+ /* Clear MIPI mode */
+ for_each_dsi_port(port, intel_dsi->ports) {
+ tmp = I915_READ(MIPI_CTRL(port));
+ tmp &= ~GLK_MIPIIO_ENABLE;
+ I915_WRITE(MIPI_CTRL(port), tmp);
+ }
+}
+
+static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
+{
+ glk_dsi_enter_low_power_mode(encoder);
+ glk_dsi_disable_mipi_io(encoder);
+}
+
+static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -701,6 +874,17 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
}
}
+static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
+ IS_BROXTON(dev_priv))
+ vlv_dsi_clear_device_ready(encoder);
+ else if (IS_GEMINILAKE(dev_priv))
+ glk_dsi_clear_device_ready(encoder);
+}
+
static void intel_dsi_post_disable(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [GLK MIPI DSI V4 4/8] drm/i915: Set the Z inversion overlap field
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (2 preceding siblings ...)
2017-02-07 12:43 ` [GLK MIPI DSI V4 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
@ 2017-02-07 12:43 ` Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 5/8] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
` (4 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Madhav Chauhan @ 2017-02-07 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula, Deepak M
From: Deepak M <m.deepak@intel.com>
Dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the older platforms,
hence setting the same in this patch.
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 0def214..bd2d180 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -561,12 +561,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
u32 temp;
-
- temp = I915_READ(VLV_CHICKEN_3);
- temp &= ~PIXEL_OVERLAP_CNT_MASK |
+ if (IS_GEN9_LP(dev_priv)) {
+ for_each_dsi_port(port, intel_dsi->ports) {
+ temp = I915_READ(MIPI_CTRL(port));
+ temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
+ intel_dsi->pixel_overlap <<
+ BXT_PIXEL_OVERLAP_CNT_SHIFT;
+ I915_WRITE(MIPI_CTRL(port), temp);
+ }
+ } else {
+ temp = I915_READ(VLV_CHICKEN_3);
+ temp &= ~PIXEL_OVERLAP_CNT_MASK |
intel_dsi->pixel_overlap <<
PIXEL_OVERLAP_CNT_SHIFT;
- I915_WRITE(VLV_CHICKEN_3, temp);
+ I915_WRITE(VLV_CHICKEN_3, temp);
+ }
}
for_each_dsi_port(port, intel_dsi->ports) {
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [GLK MIPI DSI V4 5/8] drm/i915/glk: Add DSI PLL divider range for glk
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (3 preceding siblings ...)
2017-02-07 12:43 ` [GLK MIPI DSI V4 4/8] drm/i915: Set the Z inversion overlap field Madhav Chauhan
@ 2017-02-07 12:43 ` Madhav Chauhan
2017-02-10 14:24 ` Ander Conselvan De Oliveira
2017-02-07 12:43 ` [GLK MIPI DSI V4 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
` (3 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Madhav Chauhan @ 2017-02-07 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula, Deepak M
From: Deepak M <m.deepak@intel.com>
PLL divider range for GLK is different than that of
BXT, hence adding the GLK range check in this patch.
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_dsi_pll.c | 20 ++++++++++++++------
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80ba02a..92071d6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8321,10 +8321,12 @@ enum {
#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
+#define BXT_DSIC_16X_BY1 (0 << 10)
#define BXT_DSIC_16X_BY2 (1 << 10)
#define BXT_DSIC_16X_BY3 (2 << 10)
#define BXT_DSIC_16X_BY4 (3 << 10)
#define BXT_DSIC_16X_MASK (3 << 10)
+#define BXT_DSIA_16X_BY1 (0 << 8)
#define BXT_DSIA_16X_BY2 (1 << 8)
#define BXT_DSIA_16X_BY3 (2 << 8)
#define BXT_DSIA_16X_BY4 (3 << 8)
@@ -8334,6 +8336,8 @@ enum {
#define BXT_DSI_PLL_RATIO_MAX 0x7D
#define BXT_DSI_PLL_RATIO_MIN 0x22
+#define GLK_DSI_PLL_RATIO_MAX 0x6F
+#define GLK_DSI_PLL_RATIO_MIN 0x22
#define BXT_DSI_PLL_RATIO_MASK 0xFF
#define BXT_REF_CLOCK_KHZ 19200
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 61440e5..2771c9c 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -430,9 +430,10 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
}
-static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
+static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
struct intel_crtc_state *config)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u8 dsi_ratio;
u32 dsi_clk;
@@ -446,11 +447,18 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
* round 'up' the result
*/
dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
- if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
- dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
+
+ if (IS_BROXTON(dev_priv) && (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
+ dsi_ratio > BXT_DSI_PLL_RATIO_MAX)) {
DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
return -ECHRNG;
- }
+ } else if (IS_GEMINILAKE(dev_priv) &&
+ (dsi_ratio < GLK_DSI_PLL_RATIO_MIN ||
+ dsi_ratio > GLK_DSI_PLL_RATIO_MAX)) {
+ DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
+ return -ECHRNG;
+ } else
+ DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
/*
* Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
@@ -462,7 +470,7 @@ static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
/* As per recommendation from hardware team,
* Prog PVD ratio =1 if dsi ratio <= 50
*/
- if (dsi_ratio <= 50)
+ if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
return 0;
@@ -522,7 +530,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_compute_dsi_pll(encoder, config);
else if (IS_GEN9_LP(dev_priv))
- return bxt_compute_dsi_pll(encoder, config);
+ return gen9lp_compute_dsi_pll(encoder, config);
return -ENODEV;
}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [GLK MIPI DSI V4 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (4 preceding siblings ...)
2017-02-07 12:43 ` [GLK MIPI DSI V4 5/8] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
@ 2017-02-07 12:43 ` Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 7/8] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
` (2 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Madhav Chauhan @ 2017-02-07 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula, Deepak M
From: Deepak M <m.deepak@intel.com>
Register MIPI_CLOCK_CTRL is applicable only
for BXT platform. Future platform have other
registers to program the escape clock dividers.
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 2771c9c..462d42d 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -491,8 +491,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
POSTING_READ(BXT_DSI_PLL_CTL);
/* Program TX, RX, Dphy clocks */
- for_each_dsi_port(port, intel_dsi->ports)
- bxt_dsi_program_clocks(encoder->base.dev, port, config);
+ if (IS_BROXTON(dev_priv)) {
+ for_each_dsi_port(port, intel_dsi->ports)
+ bxt_dsi_program_clocks(encoder->base.dev, port, config);
+ }
/* Enable DSI PLL */
val = I915_READ(BXT_DSI_PLL_ENABLE);
@@ -556,19 +558,22 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
bxt_disable_dsi_pll(encoder);
}
-static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
+static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
+ enum port port)
{
u32 tmp;
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
/* Clear old configurations */
- tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
- tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
- tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
- tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
- I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+ if (IS_BROXTON(dev_priv)) {
+ tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
+ tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
+ tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
+ tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
+ I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+ }
I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
}
@@ -577,7 +582,7 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (IS_GEN9_LP(dev_priv))
- bxt_dsi_reset_clocks(encoder, port);
+ gen9lp_dsi_reset_clocks(encoder, port);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_reset_clocks(encoder, port);
}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [GLK MIPI DSI V4 7/8] drm/i915/glk: Program txesc clock divider for GLK
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (5 preceding siblings ...)
2017-02-07 12:43 ` [GLK MIPI DSI V4 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
@ 2017-02-07 12:43 ` Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 8/8] drm/i915/glk: Validate only DSI PORT A PLL divider Madhav Chauhan
2017-02-07 13:24 ` ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev4) Patchwork
8 siblings, 0 replies; 16+ messages in thread
From: Madhav Chauhan @ 2017-02-07 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula, Deepak M
From: Deepak M <m.deepak@intel.com>
v2: Addressed Jani's Review comments(renamed bit field macros)
Txesc clock divider is calculated and programmed
for geminilake platform.
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++
drivers/gpu/drm/i915/intel_dsi_pll.c | 61 ++++++++++++++++++++++++++++++++++--
2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 92071d6..37121f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8235,6 +8235,11 @@ enum {
#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
+#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
+#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
+#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
+#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
+
/* BXT MIPI clock controls */
#define BXT_MAX_VAR_OUTPUT_KHZ 39500
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 462d42d..b1cc006 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -372,6 +372,53 @@ static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
ESCAPE_CLOCK_DIVIDER_SHIFT);
}
+static void glk_dsi_program_esc_clock(struct drm_device *dev,
+ const struct intel_crtc_state *config)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ u32 dsi_rate = 0;
+ u32 pll_ratio = 0;
+ u32 ddr_clk = 0;
+ u32 div1_value = 0;
+ u32 div2_value = 0;
+ u32 txesc1_div = 0;
+ u32 txesc2_div = 0;
+
+ pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
+
+ dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
+
+ ddr_clk = dsi_rate / 2;
+
+ /* Variable divider value */
+ div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
+
+ /* Calculate TXESC1 divider */
+ if (div1_value <= 10)
+ txesc1_div = div1_value;
+ else if ((div1_value > 10) && (div1_value <= 20))
+ txesc1_div = DIV_ROUND_UP(div1_value, 2);
+ else if ((div1_value > 20) && (div1_value <= 30))
+ txesc1_div = DIV_ROUND_UP(div1_value, 4);
+ else if ((div1_value > 30) && (div1_value <= 40))
+ txesc1_div = DIV_ROUND_UP(div1_value, 6);
+ else if ((div1_value > 40) && (div1_value <= 50))
+ txesc1_div = DIV_ROUND_UP(div1_value, 8);
+ else
+ txesc1_div = 10;
+
+ /* Calculate TXESC2 divider */
+ div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
+
+ if (div2_value < 10)
+ txesc2_div = div2_value;
+ else
+ txesc2_div = 10;
+
+ I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK);
+ I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK);
+}
+
/* Program BXT Mipi clocks and dividers */
static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
const struct intel_crtc_state *config)
@@ -476,7 +523,7 @@ static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
return 0;
}
-static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
+static void gen9lp_enable_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -494,6 +541,8 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
if (IS_BROXTON(dev_priv)) {
for_each_dsi_port(port, intel_dsi->ports)
bxt_dsi_program_clocks(encoder->base.dev, port, config);
+ } else {
+ glk_dsi_program_esc_clock(encoder->base.dev, config);
}
/* Enable DSI PLL */
@@ -545,7 +594,7 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder,
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_enable_dsi_pll(encoder, config);
else if (IS_GEN9_LP(dev_priv))
- bxt_enable_dsi_pll(encoder, config);
+ gen9lp_enable_dsi_pll(encoder, config);
}
void intel_disable_dsi_pll(struct intel_encoder *encoder)
@@ -573,6 +622,14 @@ static void gen9lp_dsi_reset_clocks(struct intel_encoder *encoder,
tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+ } else {
+ tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
+ tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
+ I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
+
+ tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
+ tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
+ I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
}
I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [GLK MIPI DSI V4 8/8] drm/i915/glk: Validate only DSI PORT A PLL divider
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (6 preceding siblings ...)
2017-02-07 12:43 ` [GLK MIPI DSI V4 7/8] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
@ 2017-02-07 12:43 ` Madhav Chauhan
2017-02-07 13:24 ` ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev4) Patchwork
8 siblings, 0 replies; 16+ messages in thread
From: Madhav Chauhan @ 2017-02-07 12:43 UTC (permalink / raw)
To: intel-gfx; +Cc: ander.conselvan.de.oliveira, jani.nikula
As per BSPEC, GLK supports MIPI DSI 8X clk only on PORT A.
Therefore only for PORT A PLL divider value should be validated.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
---
drivers/gpu/drm/i915/intel_dsi_pll.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index b1cc006..11c2a1c 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -206,17 +206,24 @@ static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
return false;
/*
- * Both dividers must be programmed with valid values even if only one
- * of the PLL is used, see BSpec/Broxton Clocks. Check this here for
+ * Dividers must be programmed with valid values. As per BSEPC, for
+ * GEMINLAKE only PORT A divider values are checked while for BXT
+ * both divider values are validated. Check this here for
* paranoia, since BIOS is known to misconfigure PLLs in this way at
* times, and since accessing DSI registers with invalid dividers
* causes a system hang.
*/
val = I915_READ(BXT_DSI_PLL_CTL);
- if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
- DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n",
- val);
- enabled = false;
+ if (IS_GEMINILAKE(dev_priv)) {
+ if (!(val & BXT_DSIA_16X_MASK)) {
+ DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
+ enabled = false;
+ }
+ } else {
+ if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
+ DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
+ enabled = false;
+ }
}
return enabled;
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev4)
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
` (7 preceding siblings ...)
2017-02-07 12:43 ` [GLK MIPI DSI V4 8/8] drm/i915/glk: Validate only DSI PORT A PLL divider Madhav Chauhan
@ 2017-02-07 13:24 ` Patchwork
8 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2017-02-07 13:24 UTC (permalink / raw)
To: Madhav Chauhan; +Cc: intel-gfx
== Series Details ==
Series: GLK MIPI DSI VIDEO MODE PATCHES (rev4)
URL : https://patchwork.freedesktop.org/series/16542/
State : failure
== Summary ==
Series 16542v4 GLK MIPI DSI VIDEO MODE PATCHES
https://patchwork.freedesktop.org/api/1.0/series/16542/revisions/4/mbox/
Test drv_hangman:
Subgroup error-state-basic:
pass -> INCOMPLETE (fi-hsw-4770)
Test kms_force_connector_basic:
Subgroup force-connector-state:
pass -> DMESG-WARN (fi-snb-2520m)
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-b:
dmesg-warn -> PASS (fi-snb-2520m)
fi-bdw-5557u total:252 pass:238 dwarn:0 dfail:0 fail:0 skip:14
fi-bsw-n3050 total:252 pass:213 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:252 pass:230 dwarn:0 dfail:0 fail:0 skip:22
fi-bxt-t5700 total:83 pass:70 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:252 pass:225 dwarn:0 dfail:0 fail:0 skip:27
fi-byt-n2820 total:252 pass:221 dwarn:0 dfail:0 fail:0 skip:31
fi-hsw-4770 total:5 pass:4 dwarn:0 dfail:0 fail:0 skip:0
fi-hsw-4770r total:252 pass:233 dwarn:0 dfail:0 fail:0 skip:19
fi-ilk-650 total:252 pass:199 dwarn:0 dfail:0 fail:0 skip:53
fi-ivb-3520m total:252 pass:231 dwarn:0 dfail:0 fail:0 skip:21
fi-ivb-3770 total:252 pass:231 dwarn:0 dfail:0 fail:0 skip:21
fi-kbl-7500u total:252 pass:229 dwarn:0 dfail:0 fail:2 skip:21
fi-skl-6260u total:252 pass:239 dwarn:0 dfail:0 fail:0 skip:13
fi-skl-6700hq total:252 pass:232 dwarn:0 dfail:0 fail:0 skip:20
fi-skl-6700k total:252 pass:227 dwarn:4 dfail:0 fail:0 skip:21
fi-skl-6770hq total:252 pass:239 dwarn:0 dfail:0 fail:0 skip:13
fi-snb-2520m total:252 pass:220 dwarn:1 dfail:0 fail:0 skip:31
fi-snb-2600 total:252 pass:220 dwarn:0 dfail:0 fail:0 skip:32
4b60513d8a00fc960a2d837fcccf6a63c861d9ec drm-tip: 2017y-02m-06d-22h-40m-55s UTC integration manifest
19d6c91 drm/i915/glk: Validate only DSI PORT A PLL divider
148161b drm/i915/glk: Program txesc clock divider for GLK
0e319d9 drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
0541e3b drm/i915/glk: Add DSI PLL divider range for glk
2ab172c drm/i915: Set the Z inversion overlap field
84af990 drm/i915/glk: Add MIPIIO Enable/disable sequence
dfa5542 drm/i915/glk: Program new MIPI DSI PHY registers for GLK
b8593e8 drm/i915/glk: Program dphy param reg for GLK
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3721/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK
2017-02-07 12:43 ` [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
@ 2017-02-08 14:53 ` Jani Nikula
2017-02-08 17:27 ` Chauhan, Madhav
0 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2017-02-08 14:53 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx; +Cc: ander.conselvan.de.oliveira, Deepak M
On Tue, 07 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> For GEMINILAKE, dphy param reg values are programmed in terms
> of HS byte clock count while for older platforms in terms of
> HS ddr clk count.
>
> v2: Added comments to clarify ddr clock count calculation
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 45 ++++++++++++++++++++----------
> 1 file changed, 31 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index 8f683b8..b3c495f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -674,11 +674,6 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
> break;
> }
>
> - /*
> - * ui(s) = 1/f [f in hz]
> - * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
> - */
> -
> /* in Kbps */
> ui_num = NS_KHZ_RATIO;
> ui_den = bitrate;
> @@ -692,19 +687,32 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
> */
> intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
>
> - /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
> + /* DDR clock period = 2 * UI
> + * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> + * UI(nsec) = 10^6 / bitrate
> + * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> + * DDR clock count = ns_value / DDR clock period
> *
> - * Since txddrclkhs_i is 2xUI, all the count values programmed in
> - * DPHY param register are divided by 2
> + * For GEMINILAKE dphy_param_reg will be programmed in terms of
> + * HS byte clock count for other platform in HS ddr clock count
Please add something like,
int mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
and use ui_num * mul instead of spreading IS_GEMINILAKE() check
everywhere.
BR,
Jani.
> *
> * prepare count
> */
> ths_prepare_ns = max(mipi_config->ths_prepare,
> mipi_config->tclk_prepare);
> - prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
> + if (IS_GEMINILAKE(dev_priv))
> + prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 8);
> + else
> + prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
>
> /* exit zero count */
> - exit_zero_cnt = DIV_ROUND_UP(
> + if (IS_GEMINILAKE(dev_priv))
> + exit_zero_cnt = DIV_ROUND_UP(
> + (ths_prepare_hszero - ths_prepare_ns) * ui_den,
> + ui_num * 8
> + );
> + else
> + exit_zero_cnt = DIV_ROUND_UP(
> (ths_prepare_hszero - ths_prepare_ns) * ui_den,
> ui_num * 2
> );
> @@ -719,13 +727,22 @@ struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
> exit_zero_cnt += 1;
>
> /* clk zero count */
> - clk_zero_cnt = DIV_ROUND_UP(
> - (tclk_prepare_clkzero - ths_prepare_ns)
> - * ui_den, 2 * ui_num);
> + if (IS_GEMINILAKE(dev_priv))
> + clk_zero_cnt = DIV_ROUND_UP(
> + (tclk_prepare_clkzero - ths_prepare_ns)
> + * ui_den, 8 * ui_num);
> + else
> + clk_zero_cnt = DIV_ROUND_UP(
> + (tclk_prepare_clkzero - ths_prepare_ns)
> + * ui_den, 2 * ui_num);
>
> /* trail count */
> tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> - trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
> +
> + if (IS_GEMINILAKE(dev_priv))
> + trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 * ui_num);
> + else
> + trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
>
> if (prepare_cnt > PREPARE_CNT_MAX ||
> exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [GLK MIPI DSI V4 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence
2017-02-07 12:43 ` [GLK MIPI DSI V4 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
@ 2017-02-08 14:58 ` Jani Nikula
2017-02-08 17:51 ` Chauhan, Madhav
0 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2017-02-08 14:58 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx; +Cc: ander.conselvan.de.oliveira, Deepak M
On Tue, 07 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> v2: Addressed Jani's Review comments(renamed bit field macros)
> v3: Jani's Review comment for aligning code to platforms and added
> wrapper functions.
> v4: Corrected enable/disable seuqence as per BSPEC
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 206 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 195 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index be81283..0def214 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
> return true;
> }
>
> +static void glk_dsi_device_ready(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + u32 tmp, val;
> +
> + /* Set the MIPI mode
> + * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
> + * Power ON MIPI IO first and then write into IO reset and LP wake bits
> + */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(MIPI_CTRL(port));
> + I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
> + }
> +
> + /* Put the IO into reset */
> + tmp = I915_READ(MIPI_CTRL(PORT_A));
> + tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> + I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> +
Since you've split glk_dsi_clear_device_ready into two functions, it
would stand to reason to also split this one accordingly.
BR,
Jani.
> + /* Program LP Wake */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(MIPI_CTRL(port));
> + tmp |= GLK_LP_WAKE;
> + I915_WRITE(MIPI_CTRL(port), tmp);
> + }
> +
> + /* Wait for Pwr ACK */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + if (intel_wait_for_register(dev_priv,
> + MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
> + GLK_MIPIIO_PORT_POWERED, 20))
> + DRM_ERROR("Power ACK not received\n");
> + }
> +
> + /* Wait for MIPI PHY status bit to set */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + if (intel_wait_for_register(dev_priv,
> + MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
> + GLK_MIPIIO_PORT_POWERED, 20))
> + DRM_ERROR("PHY is not ON\n");
> + }
> +
> + /* Get IO out of reset */
> + tmp = I915_READ(MIPI_CTRL(PORT_A));
> + I915_WRITE(MIPI_CTRL(PORT_A), tmp | GLK_MIPIIO_RESET_RELEASED);
> +
> + /* Get IO out of Low power state*/
> + for_each_dsi_port(port, intel_dsi->ports) {
> + if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= DEVICE_READY;
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> + usleep_range(10, 15);
> + }
> +
> + /* Enter ULPS */
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= (ULPS_STATE_ENTER | DEVICE_READY);
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> + /* Wait for ULPS Not active */
> + if (intel_wait_for_register(dev_priv,
> + MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
> + GLK_ULPS_NOT_ACTIVE, 20))
> +
> + /* Exit ULPS */
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= (ULPS_STATE_EXIT | DEVICE_READY);
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> + /* Enter Normal Mode */
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> +
> + tmp = I915_READ(MIPI_CTRL(port));
> + tmp &= ~GLK_LP_WAKE;
> + I915_WRITE(MIPI_CTRL(port), tmp);
> + }
> +
> + /* Wait for Stop state */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + if (intel_wait_for_register(dev_priv,
> + MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
> + GLK_DATA_LANE_STOP_STATE, 20))
> + DRM_ERROR("Date lane not in STOP state\n");
> + }
> +
> + /* Wait for AFE LATCH */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + if (intel_wait_for_register(dev_priv,
> + BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
> + AFE_LATCHOUT, 20))
> + DRM_ERROR("D-PHY not entering LP-11 state\n");
> + }
> +}
> +
> static void bxt_dsi_device_ready(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@ -442,8 +545,10 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_device_ready(encoder);
> - else if (IS_GEN9_LP(dev_priv))
> + else if (IS_BROXTON(dev_priv))
> bxt_dsi_device_ready(encoder);
> + else if (IS_GEMINILAKE(dev_priv))
> + glk_dsi_device_ready(encoder);
> }
>
> static void intel_dsi_port_enable(struct intel_encoder *encoder)
> @@ -637,18 +742,20 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
> msleep(2);
> }
>
> - for_each_dsi_port(port, intel_dsi->ports) {
> - /* Panel commands can be sent when clock is in LP11 */
> - I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> + if (!IS_GEMINILAKE(dev_priv)) {
> + for_each_dsi_port(port, intel_dsi->ports) {
> + /* Panel commands can be sent when clock is in LP11 */
> + I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
>
> - intel_dsi_reset_clocks(encoder, port);
> - I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> + intel_dsi_reset_clocks(encoder, port);
> + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
>
> - temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> - temp &= ~VID_MODE_FORMAT_MASK;
> - I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
> + temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> + temp &= ~VID_MODE_FORMAT_MASK;
> + I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
>
> - I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> + I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> + }
> }
> /* if disable packets are sent before sending shutdown packet then in
> * some next enable sequence send turn on packet error is observed */
> @@ -658,7 +765,73 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
> wait_for_dsi_fifo_empty(intel_dsi, port);
> }
>
> -static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> +static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + u32 val;
> +
> + /* Enter ULPS */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + val = I915_READ(MIPI_DEVICE_READY(port));
> + val &= ~ULPS_STATE_MASK;
> + val |= (ULPS_STATE_ENTER | DEVICE_READY);
> + I915_WRITE(MIPI_DEVICE_READY(port), val);
> + }
> +
> + /* Wait for MIPI PHY status bit to unset */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + if (intel_wait_for_register(dev_priv,
> + MIPI_CTRL(port),
> + GLK_PHY_STATUS_PORT_READY, 0, 20))
> + DRM_ERROR("PHY is not turning OFF\n");
> + }
> +
> + /* Wait for Pwr ACK bit to unset */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + if (intel_wait_for_register(dev_priv,
> + MIPI_CTRL(port),
> + GLK_MIPIIO_PORT_POWERED, 0, 20))
> + DRM_ERROR("MIPI IO Port is not powergated\n");
> + }
> +}
> +
> +static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + u32 tmp;
> +
> + /* Put the IO into reset */
> + tmp = I915_READ(MIPI_CTRL(PORT_A));
> + tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> + I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> +
> + /* Wait for MIPI PHY status bit to unset */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + if (intel_wait_for_register(dev_priv,
> + MIPI_CTRL(port),
> + GLK_PHY_STATUS_PORT_READY, 0, 20))
> + DRM_ERROR("PHY is not turning OFF\n");
> + }
> +
> + /* Clear MIPI mode */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(MIPI_CTRL(port));
> + tmp &= ~GLK_MIPIIO_ENABLE;
> + I915_WRITE(MIPI_CTRL(port), tmp);
> + }
> +}
> +
> +static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
> +{
> + glk_dsi_enter_low_power_mode(encoder);
> + glk_dsi_disable_mipi_io(encoder);
> +}
> +
> +static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> @@ -701,6 +874,17 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> }
> }
>
> +static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> + IS_BROXTON(dev_priv))
> + vlv_dsi_clear_device_ready(encoder);
> + else if (IS_GEMINILAKE(dev_priv))
> + glk_dsi_clear_device_ready(encoder);
> +}
> +
> static void intel_dsi_post_disable(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK
2017-02-08 14:53 ` Jani Nikula
@ 2017-02-08 17:27 ` Chauhan, Madhav
0 siblings, 0 replies; 16+ messages in thread
From: Chauhan, Madhav @ 2017-02-08 17:27 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Conselvan De Oliveira, Ander, Deepak M
> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, February 8, 2017 8:24 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> <indranil.mukherjee@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
> Saarinen, Jani <jani.saarinen@intel.com>; Conselvan De Oliveira, Ander
> <ander.conselvan.de.oliveira@intel.com>; Deepak M
> <m.deepak@intel.com>; Chauhan, Madhav <madhav.chauhan@intel.com>
> Subject: Re: [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for
> GLK
>
> On Tue, 07 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > From: Deepak M <m.deepak@intel.com>
> >
> > For GEMINILAKE, dphy param reg values are programmed in terms of HS
> > byte clock count while for older platforms in terms of HS ddr clk
> > count.
> >
> > v2: Added comments to clarify ddr clock count calculation
> >
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 45
> > ++++++++++++++++++++----------
> > 1 file changed, 31 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > index 8f683b8..b3c495f 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > @@ -674,11 +674,6 @@ struct drm_panel *vbt_panel_init(struct intel_dsi
> *intel_dsi, u16 panel_id)
> > break;
> > }
> >
> > - /*
> > - * ui(s) = 1/f [f in hz]
> > - * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
> > - */
> > -
> > /* in Kbps */
> > ui_num = NS_KHZ_RATIO;
> > ui_den = bitrate;
> > @@ -692,19 +687,32 @@ struct drm_panel *vbt_panel_init(struct intel_dsi
> *intel_dsi, u16 panel_id)
> > */
> > intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 *
> ui_num);
> >
> > - /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
> > + /* DDR clock period = 2 * UI
> > + * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> > + * UI(nsec) = 10^6 / bitrate
> > + * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> > + * DDR clock count = ns_value / DDR clock period
> > *
> > - * Since txddrclkhs_i is 2xUI, all the count values programmed in
> > - * DPHY param register are divided by 2
> > + * For GEMINILAKE dphy_param_reg will be programmed in terms of
> > + * HS byte clock count for other platform in HS ddr clock count
>
> Please add something like,
>
> int mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
>
> and use ui_num * mul instead of spreading IS_GEMINILAKE() check
> everywhere.
Correct, that's better way. Will include this in next series.
>
> BR,
> Jani.
>
>
> > *
> > * prepare count
> > */
> > ths_prepare_ns = max(mipi_config->ths_prepare,
> > mipi_config->tclk_prepare);
> > - prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num *
> 2);
> > + if (IS_GEMINILAKE(dev_priv))
> > + prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
> ui_num * 8);
> > + else
> > + prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
> ui_num * 2);
> >
> > /* exit zero count */
> > - exit_zero_cnt = DIV_ROUND_UP(
> > + if (IS_GEMINILAKE(dev_priv))
> > + exit_zero_cnt = DIV_ROUND_UP(
> > + (ths_prepare_hszero - ths_prepare_ns) *
> ui_den,
> > + ui_num * 8
> > + );
> > + else
> > + exit_zero_cnt = DIV_ROUND_UP(
> > (ths_prepare_hszero - ths_prepare_ns) *
> ui_den,
> > ui_num * 2
> > );
> > @@ -719,13 +727,22 @@ struct drm_panel *vbt_panel_init(struct intel_dsi
> *intel_dsi, u16 panel_id)
> > exit_zero_cnt += 1;
> >
> > /* clk zero count */
> > - clk_zero_cnt = DIV_ROUND_UP(
> > - (tclk_prepare_clkzero - ths_prepare_ns)
> > - * ui_den, 2 * ui_num);
> > + if (IS_GEMINILAKE(dev_priv))
> > + clk_zero_cnt = DIV_ROUND_UP(
> > + (tclk_prepare_clkzero - ths_prepare_ns)
> > + * ui_den, 8 * ui_num);
> > + else
> > + clk_zero_cnt = DIV_ROUND_UP(
> > + (tclk_prepare_clkzero - ths_prepare_ns)
> > + * ui_den, 2 * ui_num);
> >
> > /* trail count */
> > tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> > - trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
> > +
> > + if (IS_GEMINILAKE(dev_priv))
> > + trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 *
> ui_num);
> > + else
> > + trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 *
> ui_num);
> >
> > if (prepare_cnt > PREPARE_CNT_MAX ||
> > exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [GLK MIPI DSI V4 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence
2017-02-08 14:58 ` Jani Nikula
@ 2017-02-08 17:51 ` Chauhan, Madhav
0 siblings, 0 replies; 16+ messages in thread
From: Chauhan, Madhav @ 2017-02-08 17:51 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Conselvan De Oliveira, Ander, Deepak M
> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, February 8, 2017 8:29 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Mukherjee, Indranil
> <indranil.mukherjee@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
> Saarinen, Jani <jani.saarinen@intel.com>; Conselvan De Oliveira, Ander
> <ander.conselvan.de.oliveira@intel.com>; Deepak M
> <m.deepak@intel.com>; Chauhan, Madhav <madhav.chauhan@intel.com>
> Subject: Re: [GLK MIPI DSI V4 3/8] drm/i915/glk: Add MIPIIO Enable/disable
> sequence
>
> On Tue, 07 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com>
> wrote:
> > From: Deepak M <m.deepak@intel.com>
> >
> > v2: Addressed Jani's Review comments(renamed bit field macros)
> > v3: Jani's Review comment for aligning code to platforms and added
> > wrapper functions.
> > v4: Corrected enable/disable seuqence as per BSPEC
> >
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dsi.c | 206
> > ++++++++++++++++++++++++++++++++++++---
> > 1 file changed, 195 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index be81283..0def214 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -357,6 +357,109 @@ static bool intel_dsi_compute_config(struct
> intel_encoder *encoder,
> > return true;
> > }
> >
> > +static void glk_dsi_device_ready(struct intel_encoder *encoder) {
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > + enum port port;
> > + u32 tmp, val;
> > +
> > + /* Set the MIPI mode
> > + * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
> > + * Power ON MIPI IO first and then write into IO reset and LP wake
> bits
> > + */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + tmp = I915_READ(MIPI_CTRL(port));
> > + I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
> > + }
> > +
> > + /* Put the IO into reset */
> > + tmp = I915_READ(MIPI_CTRL(PORT_A));
> > + tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> > + I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> > +
>
> Since you've split glk_dsi_clear_device_ready into two functions, it would
> stand to reason to also split this one accordingly.
glk_dsi_clear_device_ready includes two steps: 7 and 8 of disable sequence mentioned in bspec that's why splitted.
While glk_dsi_device_ready is *ONLY* doing step 4 (enable IO).
>
> BR,
> Jani.
>
> > + /* Program LP Wake */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + tmp = I915_READ(MIPI_CTRL(port));
> > + tmp |= GLK_LP_WAKE;
> > + I915_WRITE(MIPI_CTRL(port), tmp);
> > + }
> > +
> > + /* Wait for Pwr ACK */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + if (intel_wait_for_register(dev_priv,
> > + MIPI_CTRL(port),
> GLK_MIPIIO_PORT_POWERED,
> > + GLK_MIPIIO_PORT_POWERED, 20))
> > + DRM_ERROR("Power ACK not received\n");
> > + }
> > +
> > + /* Wait for MIPI PHY status bit to set */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + if (intel_wait_for_register(dev_priv,
> > + MIPI_CTRL(port),
> GLK_MIPIIO_PORT_POWERED,
> > + GLK_MIPIIO_PORT_POWERED, 20))
> > + DRM_ERROR("PHY is not ON\n");
> > + }
> > +
> > + /* Get IO out of reset */
> > + tmp = I915_READ(MIPI_CTRL(PORT_A));
> > + I915_WRITE(MIPI_CTRL(PORT_A), tmp |
> GLK_MIPIIO_RESET_RELEASED);
> > +
> > + /* Get IO out of Low power state*/
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + if (!(I915_READ(MIPI_DEVICE_READY(port)) &
> DEVICE_READY)) {
> > + val = I915_READ(MIPI_DEVICE_READY(port));
> > + val &= ~ULPS_STATE_MASK;
> > + val |= DEVICE_READY;
> > + I915_WRITE(MIPI_DEVICE_READY(port), val);
> > + usleep_range(10, 15);
> > + }
> > +
> > + /* Enter ULPS */
> > + val = I915_READ(MIPI_DEVICE_READY(port));
> > + val &= ~ULPS_STATE_MASK;
> > + val |= (ULPS_STATE_ENTER | DEVICE_READY);
> > + I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +
> > + /* Wait for ULPS Not active */
> > + if (intel_wait_for_register(dev_priv,
> > + MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE,
> > + GLK_ULPS_NOT_ACTIVE, 20))
> > +
> > + /* Exit ULPS */
> > + val = I915_READ(MIPI_DEVICE_READY(port));
> > + val &= ~ULPS_STATE_MASK;
> > + val |= (ULPS_STATE_EXIT | DEVICE_READY);
> > + I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +
> > + /* Enter Normal Mode */
> > + val = I915_READ(MIPI_DEVICE_READY(port));
> > + val &= ~ULPS_STATE_MASK;
> > + val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
> > + I915_WRITE(MIPI_DEVICE_READY(port), val);
> > +
> > + tmp = I915_READ(MIPI_CTRL(port));
> > + tmp &= ~GLK_LP_WAKE;
> > + I915_WRITE(MIPI_CTRL(port), tmp);
> > + }
> > +
> > + /* Wait for Stop state */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + if (intel_wait_for_register(dev_priv,
> > + MIPI_CTRL(port),
> GLK_DATA_LANE_STOP_STATE,
> > + GLK_DATA_LANE_STOP_STATE, 20))
> > + DRM_ERROR("Date lane not in STOP state\n");
> > + }
> > +
> > + /* Wait for AFE LATCH */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + if (intel_wait_for_register(dev_priv,
> > + BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
> > + AFE_LATCHOUT, 20))
> > + DRM_ERROR("D-PHY not entering LP-11 state\n");
> > + }
> > +}
> > +
> > static void bxt_dsi_device_ready(struct intel_encoder *encoder) {
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> @@
> > -442,8 +545,10 @@ static void intel_dsi_device_ready(struct
> > intel_encoder *encoder)
> >
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > vlv_dsi_device_ready(encoder);
> > - else if (IS_GEN9_LP(dev_priv))
> > + else if (IS_BROXTON(dev_priv))
> > bxt_dsi_device_ready(encoder);
> > + else if (IS_GEMINILAKE(dev_priv))
> > + glk_dsi_device_ready(encoder);
> > }
> >
> > static void intel_dsi_port_enable(struct intel_encoder *encoder) @@
> > -637,18 +742,20 @@ static void intel_dsi_disable(struct intel_encoder
> *encoder)
> > msleep(2);
> > }
> >
> > - for_each_dsi_port(port, intel_dsi->ports) {
> > - /* Panel commands can be sent when clock is in LP11 */
> > - I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> > + if (!IS_GEMINILAKE(dev_priv)) {
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + /* Panel commands can be sent when clock is in LP11
> */
> > + I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
> >
> > - intel_dsi_reset_clocks(encoder, port);
> > - I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> > + intel_dsi_reset_clocks(encoder, port);
> > + I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
> >
> > - temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> > - temp &= ~VID_MODE_FORMAT_MASK;
> > - I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
> > + temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
> > + temp &= ~VID_MODE_FORMAT_MASK;
> > + I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
> >
> > - I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> > + I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
> > + }
> > }
> > /* if disable packets are sent before sending shutdown packet then in
> > * some next enable sequence send turn on packet error is observed
> > */ @@ -658,7 +765,73 @@ static void intel_dsi_disable(struct
> intel_encoder *encoder)
> > wait_for_dsi_fifo_empty(intel_dsi, port); }
> >
> > -static void intel_dsi_clear_device_ready(struct intel_encoder
> > *encoder)
> > +static void glk_dsi_enter_low_power_mode(struct intel_encoder
> > +*encoder) {
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > + enum port port;
> > + u32 val;
> > +
> > + /* Enter ULPS */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + val = I915_READ(MIPI_DEVICE_READY(port));
> > + val &= ~ULPS_STATE_MASK;
> > + val |= (ULPS_STATE_ENTER | DEVICE_READY);
> > + I915_WRITE(MIPI_DEVICE_READY(port), val);
> > + }
> > +
> > + /* Wait for MIPI PHY status bit to unset */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + if (intel_wait_for_register(dev_priv,
> > + MIPI_CTRL(port),
> > + GLK_PHY_STATUS_PORT_READY, 0,
> 20))
> > + DRM_ERROR("PHY is not turning OFF\n");
> > + }
> > +
> > + /* Wait for Pwr ACK bit to unset */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + if (intel_wait_for_register(dev_priv,
> > + MIPI_CTRL(port),
> > + GLK_MIPIIO_PORT_POWERED, 0,
> 20))
> > + DRM_ERROR("MIPI IO Port is not powergated\n");
> > + }
> > +}
> > +
> > +static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) {
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > + enum port port;
> > + u32 tmp;
> > +
> > + /* Put the IO into reset */
> > + tmp = I915_READ(MIPI_CTRL(PORT_A));
> > + tmp &= ~GLK_MIPIIO_RESET_RELEASED;
> > + I915_WRITE(MIPI_CTRL(PORT_A), tmp);
> > +
> > + /* Wait for MIPI PHY status bit to unset */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + if (intel_wait_for_register(dev_priv,
> > + MIPI_CTRL(port),
> > + GLK_PHY_STATUS_PORT_READY, 0,
> 20))
> > + DRM_ERROR("PHY is not turning OFF\n");
> > + }
> > +
> > + /* Clear MIPI mode */
> > + for_each_dsi_port(port, intel_dsi->ports) {
> > + tmp = I915_READ(MIPI_CTRL(port));
> > + tmp &= ~GLK_MIPIIO_ENABLE;
> > + I915_WRITE(MIPI_CTRL(port), tmp);
> > + }
> > +}
> > +
> > +static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
> > +{
> > + glk_dsi_enter_low_power_mode(encoder);
> > + glk_dsi_disable_mipi_io(encoder);
> > +}
> > +
> > +static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
> > {
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@
> > -701,6 +874,17 @@ static void intel_dsi_clear_device_ready(struct
> intel_encoder *encoder)
> > }
> > }
> >
> > +static void intel_dsi_clear_device_ready(struct intel_encoder
> > +*encoder) {
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +
> > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> > + IS_BROXTON(dev_priv))
> > + vlv_dsi_clear_device_ready(encoder);
> > + else if (IS_GEMINILAKE(dev_priv))
> > + glk_dsi_clear_device_ready(encoder);
> > +}
> > +
> > static void intel_dsi_post_disable(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config,
> > struct drm_connector_state *conn_state)
>
> --
> Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [GLK MIPI DSI V4 5/8] drm/i915/glk: Add DSI PLL divider range for glk
2017-02-07 12:43 ` [GLK MIPI DSI V4 5/8] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
@ 2017-02-10 14:24 ` Ander Conselvan De Oliveira
2017-02-13 11:14 ` Chauhan, Madhav
0 siblings, 1 reply; 16+ messages in thread
From: Ander Conselvan De Oliveira @ 2017-02-10 14:24 UTC (permalink / raw)
To: Madhav Chauhan, intel-gfx; +Cc: jani.nikula, Deepak M
On Tue, 2017-02-07 at 18:13 +0530, Madhav Chauhan wrote:
> From: Deepak M <m.deepak@intel.com>
>
> PLL divider range for GLK is different than that of
> BXT, hence adding the GLK range check in this patch.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_dsi_pll.c | 20 ++++++++++++++------
> 2 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 80ba02a..92071d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8321,10 +8321,12 @@ enum {
> #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
> #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define BXT_DSIC_16X_BY1 (0 << 10)
> #define BXT_DSIC_16X_BY2 (1 << 10)
> #define BXT_DSIC_16X_BY3 (2 << 10)
> #define BXT_DSIC_16X_BY4 (3 << 10)
> #define BXT_DSIC_16X_MASK (3 << 10)
> +#define BXT_DSIA_16X_BY1 (0 << 8)
> #define BXT_DSIA_16X_BY2 (1 << 8)
> #define BXT_DSIA_16X_BY3 (2 << 8)
> #define BXT_DSIA_16X_BY4 (3 << 8)
> @@ -8334,6 +8336,8 @@ enum {
>
> #define BXT_DSI_PLL_RATIO_MAX 0x7D
> #define BXT_DSI_PLL_RATIO_MIN 0x22
> +#define GLK_DSI_PLL_RATIO_MAX 0x6F
> +#define GLK_DSI_PLL_RATIO_MIN 0x22
> #define BXT_DSI_PLL_RATIO_MASK 0xFF
> #define BXT_REF_CLOCK_KHZ 19200
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 61440e5..2771c9c 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -430,9 +430,10 @@ static void bxt_dsi_program_clocks(struct drm_device
> *dev, enum port port,
> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> }
>
> -static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
> +static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
> struct intel_crtc_state *config)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u8 dsi_ratio;
> u32 dsi_clk;
> @@ -446,11 +447,18 @@ static int bxt_compute_dsi_pll(struct intel_encoder
> *encoder,
> * round 'up' the result
> */
> dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
> - if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> - dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
> +
> + if (IS_BROXTON(dev_priv) && (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> + dsi_ratio > BXT_DSI_PLL_RATIO_MAX)) {
> DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
> return -ECHRNG;
> - }
> + } else if (IS_GEMINILAKE(dev_priv) &&
> + (dsi_ratio < GLK_DSI_PLL_RATIO_MIN ||
> + dsi_ratio > GLK_DSI_PLL_RATIO_MAX)) {
> + DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
> + return -ECHRNG;
> + } else
> + DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
u32 ratio_min, ratio_max;
if (IS_BROXTON()) {
ratio_min = ...
ratio_max = ...
} else if (IS_GEMINILAKE()) {
ratio_min = ...
ratio_max = ...
}
if (dsi_ratio < ratio_min || dsi_ratio > ratio_max) {
...
Ander
>
> /*
> * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
> @@ -462,7 +470,7 @@ static int bxt_compute_dsi_pll(struct intel_encoder
> *encoder,
> /* As per recommendation from hardware team,
> * Prog PVD ratio =1 if dsi ratio <= 50
> */
> - if (dsi_ratio <= 50)
> + if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
> config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
>
> return 0;
> @@ -522,7 +530,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return vlv_compute_dsi_pll(encoder, config);
> else if (IS_GEN9_LP(dev_priv))
> - return bxt_compute_dsi_pll(encoder, config);
> + return gen9lp_compute_dsi_pll(encoder, config);
>
> return -ENODEV;
> }
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [GLK MIPI DSI V4 5/8] drm/i915/glk: Add DSI PLL divider range for glk
2017-02-10 14:24 ` Ander Conselvan De Oliveira
@ 2017-02-13 11:14 ` Chauhan, Madhav
0 siblings, 0 replies; 16+ messages in thread
From: Chauhan, Madhav @ 2017-02-13 11:14 UTC (permalink / raw)
To: 'Ander Conselvan De Oliveira', intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Ander Conselvan De Oliveira [mailto:conselvan2@gmail.com]
> Sent: Friday, February 10, 2017 7:54 PM
> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Deepak M <m.deepak@intel.com>
> Subject: Re: [Intel-gfx] [GLK MIPI DSI V4 5/8] drm/i915/glk: Add DSI PLL
> divider range for glk
>
> On Tue, 2017-02-07 at 18:13 +0530, Madhav Chauhan wrote:
> > From: Deepak M <m.deepak@intel.com>
> >
> > PLL divider range for GLK is different than that of BXT, hence adding
> > the GLK range check in this patch.
> >
> > Signed-off-by: Deepak M <m.deepak@intel.com>
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > drivers/gpu/drm/i915/intel_dsi_pll.c | 20 ++++++++++++++------
> > 2 files changed, 18 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 80ba02a..92071d6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8321,10 +8321,12 @@ enum {
> > #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
> > #define BXT_DSI_PLL_PVD_RATIO_MASK (3 <<
> BXT_DSI_PLL_PVD_RATIO_SHIFT)
> > #define BXT_DSI_PLL_PVD_RATIO_1 (1 <<
> BXT_DSI_PLL_PVD_RATIO_SHIFT)
> > +#define BXT_DSIC_16X_BY1 (0 << 10)
> > #define BXT_DSIC_16X_BY2 (1 << 10)
> > #define BXT_DSIC_16X_BY3 (2 << 10)
> > #define BXT_DSIC_16X_BY4 (3 << 10)
> > #define BXT_DSIC_16X_MASK (3 << 10)
> > +#define BXT_DSIA_16X_BY1 (0 << 8)
> > #define BXT_DSIA_16X_BY2 (1 << 8)
> > #define BXT_DSIA_16X_BY3 (2 << 8)
> > #define BXT_DSIA_16X_BY4 (3 << 8)
> > @@ -8334,6 +8336,8 @@ enum {
> >
> > #define BXT_DSI_PLL_RATIO_MAX 0x7D
> > #define BXT_DSI_PLL_RATIO_MIN 0x22
> > +#define GLK_DSI_PLL_RATIO_MAX 0x6F
> > +#define GLK_DSI_PLL_RATIO_MIN 0x22
> > #define BXT_DSI_PLL_RATIO_MASK 0xFF
> > #define BXT_REF_CLOCK_KHZ 19200
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > index 61440e5..2771c9c 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > @@ -430,9 +430,10 @@ static void bxt_dsi_program_clocks(struct
> > drm_device *dev, enum port port,
> > I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> > }
> >
> > -static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
> > +static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
> > struct intel_crtc_state *config)
> > {
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > u8 dsi_ratio;
> > u32 dsi_clk;
> > @@ -446,11 +447,18 @@ static int bxt_compute_dsi_pll(struct
> > intel_encoder *encoder,
> > * round 'up' the result
> > */
> > dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
> > - if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> > - dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
> > +
> > + if (IS_BROXTON(dev_priv) && (dsi_ratio < BXT_DSI_PLL_RATIO_MIN
> ||
> > + dsi_ratio > BXT_DSI_PLL_RATIO_MAX)) {
> > DRM_ERROR("Cant get a suitable ratio from DSI PLL
> ratios\n");
> > return -ECHRNG;
> > - }
> > + } else if (IS_GEMINILAKE(dev_priv) &&
> > + (dsi_ratio < GLK_DSI_PLL_RATIO_MIN ||
> > + dsi_ratio > GLK_DSI_PLL_RATIO_MAX)) {
> > + DRM_ERROR("Cant get a suitable ratio from DSI PLL
> ratios\n");
> > + return -ECHRNG;
> > + } else
> > + DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
>
>
> u32 ratio_min, ratio_max;
>
> if (IS_BROXTON()) {
> ratio_min = ...
> ratio_max = ...
> } else if (IS_GEMINILAKE()) {
> ratio_min = ...
> ratio_max = ...
> }
>
> if (dsi_ratio < ratio_min || dsi_ratio > ratio_max) {
> ...
>
Thanks Ander for review. Will include these changes in next series.
>
> Ander
>
> >
> > /*
> > * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
> @@
> > -462,7 +470,7 @@ static int bxt_compute_dsi_pll(struct intel_encoder
> > *encoder,
> > /* As per recommendation from hardware team,
> > * Prog PVD ratio =1 if dsi ratio <= 50
> > */
> > - if (dsi_ratio <= 50)
> > + if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
> > config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
> >
> > return 0;
> > @@ -522,7 +530,7 @@ int intel_compute_dsi_pll(struct intel_encoder
> *encoder,
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > return vlv_compute_dsi_pll(encoder, config);
> > else if (IS_GEN9_LP(dev_priv))
> > - return bxt_compute_dsi_pll(encoder, config);
> > + return gen9lp_compute_dsi_pll(encoder, config);
> >
> > return -ENODEV;
> > }
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^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2017-02-13 11:14 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-02-07 12:43 [GLK MIPI DSI V4 0/8] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
2017-02-08 14:53 ` Jani Nikula
2017-02-08 17:27 ` Chauhan, Madhav
2017-02-07 12:43 ` [GLK MIPI DSI V4 2/8] drm/i915/glk: Program new MIPI DSI PHY registers " Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 3/8] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2017-02-08 14:58 ` Jani Nikula
2017-02-08 17:51 ` Chauhan, Madhav
2017-02-07 12:43 ` [GLK MIPI DSI V4 4/8] drm/i915: Set the Z inversion overlap field Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 5/8] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2017-02-10 14:24 ` Ander Conselvan De Oliveira
2017-02-13 11:14 ` Chauhan, Madhav
2017-02-07 12:43 ` [GLK MIPI DSI V4 6/8] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 7/8] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2017-02-07 12:43 ` [GLK MIPI DSI V4 8/8] drm/i915/glk: Validate only DSI PORT A PLL divider Madhav Chauhan
2017-02-07 13:24 ` ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev4) Patchwork
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