From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49135) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1brmTc-0002ha-Vq for qemu-devel@nongnu.org; Wed, 05 Oct 2016 09:43:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1brmTZ-00088y-4n for qemu-devel@nongnu.org; Wed, 05 Oct 2016 09:43:15 -0400 Received: from mail-lf0-x22e.google.com ([2a00:1450:4010:c07::22e]:33998) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1brmTY-00088g-Mu for qemu-devel@nongnu.org; Wed, 05 Oct 2016 09:43:13 -0400 Received: by mail-lf0-x22e.google.com with SMTP id b81so92826722lfe.1 for ; Wed, 05 Oct 2016 06:43:12 -0700 (PDT) References: <1474048017-26696-1-git-send-email-rth@twiddle.net> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1474048017-26696-1-git-send-email-rth@twiddle.net> Date: Wed, 05 Oct 2016 14:43:09 +0100 Message-ID: <87a8eisyhe.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v4 00/35] cmpxchg-based emulation of atomics List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org Richard Henderson writes: > Rebased on top of Paolo's safe-work series, which means > that we now have cpu_exec_step_atomic for system mode as > well as linux-user. This should fix the problems with > atomic access to notdirty pages that have been reported. > > Folded in some feedback from Alex from v3. I noticed some bits missing from my v3 feedback. I'm assuming the comments came after you cut this branch? > > A complete tree may be found at > > git://github.com/rth7680/qemu.git atomic-4 I've finished my pass of this series. Looking forward to v5, I think we are pretty good shape for a merge once the final niggles are sorted. Will you take it in via your tree or through one of the other TCG maintainers? > > > r~ > > > Emilio G. Cota (18): > atomics: add atomic_xor > atomics: add atomic_op_fetch variants > target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers > target-i386: emulate LOCK'ed OP instructions using atomic helpers > target-i386: emulate LOCK'ed INC using atomic helper > target-i386: emulate LOCK'ed NOT using atomic helper > target-i386: emulate LOCK'ed NEG using cmpxchg helper > target-i386: emulate LOCK'ed XADD using atomic helper > target-i386: emulate LOCK'ed BTX ops using atomic helpers > target-i386: emulate XCHG using atomic helper > target-i386: remove helper_lock() > tests: add atomic_add-bench > target-arm: emulate LL/SC using cmpxchg helpers > target-arm: emulate SWP with atomic_xchg helper > target-arm: emulate aarch64's LL/SC using cmpxchg helpers > linux-user: remove handling of ARM's EXCP_STREX > linux-user: remove handling of aarch64's EXCP_STREX > target-arm: remove EXCP_STREX + cpu_exclusive_{test, info} > > Richard Henderson (17): > exec: Avoid direct references to Int128 parts > int128: Use __int128 if available > int128: Add int128_make128 > tcg: Add EXCP_ATOMIC > HACK: Always enable parallel_cpus > cputlb: Replace SHIFT with DATA_SIZE > cputlb: Move probe_write out of softmmu_template.h > cputlb: Remove includes from softmmu_template.h > cputlb: Move most of iotlb code out of line > cputlb: Tidy some macros > tcg: Add atomic helpers > tcg: Add atomic128 helpers > tcg: Add CONFIG_ATOMIC64 > tcg: Emit barriers with parallel_cpus > target-arm: Rearrange aa32 load and store functions > target-alpha: Introduce MMU_PHYS_IDX > target-alpha: Emulate LL/SC using cmpxchg helpers > > Makefile.objs | 1 - > Makefile.target | 1 + > atomic_template.h | 211 +++++++++++++++++++++++++ > configure | 62 +++++++- > cpu-exec-common.c | 6 + > cpu-exec.c | 30 ++++ > cpus.c | 2 + > cputlb.c | 203 ++++++++++++++++++++++-- > exec.c | 4 +- > include/exec/cpu-all.h | 1 + > include/exec/exec-all.h | 1 + > include/qemu-common.h | 1 + > include/qemu/atomic.h | 40 ++++- > include/qemu/int128.h | 171 +++++++++++++++++++- > linux-user/main.c | 312 ++++++------------------------------ > softmmu_template.h | 104 ++---------- > target-alpha/cpu.h | 22 +-- > target-alpha/helper.c | 14 +- > target-alpha/helper.h | 9 -- > target-alpha/machine.c | 2 - > target-alpha/mem_helper.c | 73 --------- > target-alpha/translate.c | 148 +++++++++-------- > target-arm/cpu.h | 17 +- > target-arm/helper-a64.c | 113 +++++++++++++ > target-arm/helper-a64.h | 2 + > target-arm/internals.h | 4 +- > target-arm/translate-a64.c | 106 ++++++------- > target-arm/translate.c | 342 ++++++++++++++------------------------- > target-arm/translate.h | 4 - > target-i386/helper.h | 4 +- > target-i386/mem_helper.c | 153 ++++++++++++------ > target-i386/translate.c | 386 +++++++++++++++++++++++++++++---------------- > tcg-runtime.c | 74 +++++++-- > tcg/tcg-op.c | 354 +++++++++++++++++++++++++++++++++++++++-- > tcg/tcg-op.h | 44 ++++++ > tcg/tcg-runtime.h | 109 +++++++++++++ > tcg/tcg.h | 85 ++++++++++ > tests/.gitignore | 1 + > tests/Makefile.include | 4 +- > tests/atomic_add-bench.c | 181 +++++++++++++++++++++ > tests/test-int128.c | 22 +-- > translate-all.c | 1 + > 42 files changed, 2336 insertions(+), 1088 deletions(-) > create mode 100644 atomic_template.h > create mode 100644 tests/atomic_add-bench.c -- Alex Bennée