[PATCH] drm/i915: More DPIO magic for CHV HDMI & DP

[PATCH] drm/i915: More DPIO magic for CHV HDMI & DP

[Vijay Purushothaman]

This patch implements latest changes in Gain, lock threshold and integer
co-efficient values using sideband r/w. Without these changes there will
be signal integrity issues for both HDMI and DP.

Change-Id: I7b7151b5ab3a52c4c912cf10602c69a7d1a70222
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Tested-by: Hong Liu <hong.liu@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |   31 ++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |   67 ++++++++++++++++++++++++----------
 2 files changed, 79 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 137c5e0..2b3f065 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1049,6 +1049,37 @@ enum punit_power_well {
 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
 
+#define _CHV_PLL_DW7_CH0		0x801c
+#define _CHV_PLL_DW7_CH1		0x803c
+#define CHV_PLL_DW7(ch) _PIPE(ch, _CHV_PLL_DW7_CH0, _CHV_PLL_DW7_CH1)
+
+#define _CHV_PLL_DW8_CH0		0x8020
+#define _CHV_PLL_DW8_CH1		0x81A0
+#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
+
+#define _CHV_PLL_DW9_CH0		0x8024
+#define _CHV_PLL_DW9_CH1		0x81A4
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
+#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
+
+#define _CHV_PLL_DW10_CH0		0x8040
+#define _CHV_PLL_DW10_CH1		0x8060
+#define CHV_PLL_DW10(ch) _PIPE(ch, _CHV_PLL_DW10_CH0, _CHV_PLL_DW10_CH1)
+
+#define _CHV_PLL_DW11_BCAST		0xC044
+#define _CHV_PLL_DW11_CH0		0x8044
+#define _CHV_PLL_DW11_CH1		0x8064
+#define CHV_PLL_DW11(ch) _PIPE(ch, _CHV_PLL_DW11_CH0, _CHV_PLL_DW11_CH1)
+
+#define _CHV_PLL_DW12_CH0		0x8048
+#define _CHV_PLL_DW12_CH1		0x8068
+#define CHV_PLL_DW12(ch) _PIPE(ch, _CHV_PLL_DW12_CH0, _CHV_PLL_DW12_CH1)
+
+#define _CHV_PLL_DW13_CH0		0x804C
+#define _CHV_PLL_DW13_CH1		0x806C
+#define CHV_PLL_DW13(ch) _PIPE(ch, _CHV_PLL_DW13_CH0, _CHV_PLL_DW13_CH1)
+
 #define _CHV_CMN_DW5_CH0               0x8114
 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
 #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c362d11e..fb27faf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6576,9 +6576,9 @@ static void chv_update_pll(struct intel_crtc *crtc)
 	int pipe = crtc->pipe;
 	int dpll_reg = DPLL(crtc->pipe);
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
-	u32 loopfilter, intcoeff;
+	u32 loopfilter, tribuf_calcntr;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
-	int refclk;
+	int vco;
 
 	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
 		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
@@ -6595,6 +6595,7 @@ static void chv_update_pll(struct intel_crtc *crtc)
 	bestm2 = crtc->config.dpll.m2 >> 22;
 	bestp1 = crtc->config.dpll.p1;
 	bestp2 = crtc->config.dpll.p2;
+	vco = crtc->config.dpll.vco;
 
 	/*
 	 * Enable Refclk and SSC
@@ -6619,31 +6620,59 @@ static void chv_update_pll(struct intel_crtc *crtc)
 			DPIO_CHV_M1_DIV_BY_2 |
 			1 << DPIO_CHV_N_DIV_SHIFT);
 
-	/* M2 fraction division */
-	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+	if (bestm2_frac) {
+		/* M2 fraction division */
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+
+		/* M2 fraction division enable */
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
+				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) &
+				DPIO_CHV_FRAC_DIV_EN);
+
+		/* Program digital lock detect threshold */
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
+				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)) |
+				(0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT));
+	} else {
+		/* M2 fraction division disable */
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
+				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) &
+				~(DPIO_CHV_FRAC_DIV_EN));
 
-	/* M2 fraction division enable */
-	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
-		       DPIO_CHV_FRAC_DIV_EN |
-		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+		/* Program digital lock detect threshold */
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
+				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)) |
+				(0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT) |
+				DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
+	}
 
 	/* Loop filter */
-	refclk = i9xx_get_refclk(&crtc->base, 0);
-	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
-		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
-	if (refclk == 100000)
-		intcoeff = 11;
-	else if (refclk == 38400)
-		intcoeff = 10;
+	if (vco == 540000)
+		loopfilter = 0x10803;
+	else if (vco <= 620000)
+		loopfilter = 0x30B05;
+	else if (vco <= 648000)
+		loopfilter = 0x30904;
+	else
+		loopfilter = 0x10803;
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port),
+			((vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW6(port)) &
+			0xFF000000) | loopfilter));
+
+	if (vco <= 620000)
+		tribuf_calcntr = 0x9;
+	else if (vco <= 648000)
+		tribuf_calcntr = 0x8;
 	else
-		intcoeff = 9;
-	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
-	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
+		tribuf_calcntr = 0;
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port),
+			((vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)) &
+			0xFFFFFF00) | tribuf_calcntr));
 
 	/* AFC Recal */
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
 			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
-			DPIO_AFC_RECAL);
+			DPIO_AFC_RECAL | DPIO_DCLKP_EN);
 
 	mutex_unlock(&dev_priv->dpio_lock);
 }
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: More DPIO magic for CHV HDMI & DP

[Ville Syrjälä]

On Fri, Jan 30, 2015 at 12:01:53AM +0530, Vijay Purushothaman wrote:
> This patch implements latest changes in Gain, lock threshold and integer
> co-efficient values using sideband r/w. Without these changes there will
> be signal integrity issues for both HDMI and DP.
> 
> Change-Id: I7b7151b5ab3a52c4c912cf10602c69a7d1a70222
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> Tested-by: Hong Liu <hong.liu@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |   31 ++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |   67 ++++++++++++++++++++++++----------
>  2 files changed, 79 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 137c5e0..2b3f065 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1049,6 +1049,37 @@ enum punit_power_well {
>  #define   DPIO_CHV_PROP_COEFF_SHIFT	0
>  #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
>  
> +#define _CHV_PLL_DW7_CH0		0x801c
> +#define _CHV_PLL_DW7_CH1		0x803c
> +#define CHV_PLL_DW7(ch) _PIPE(ch, _CHV_PLL_DW7_CH0, _CHV_PLL_DW7_CH1)

unused

> +
> +#define _CHV_PLL_DW8_CH0		0x8020
> +#define _CHV_PLL_DW8_CH1		0x81A0
> +#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
> +
> +#define _CHV_PLL_DW9_CH0		0x8024
> +#define _CHV_PLL_DW9_CH1		0x81A4
> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
> +#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
> +
> +#define _CHV_PLL_DW10_CH0		0x8040
> +#define _CHV_PLL_DW10_CH1		0x8060
> +#define CHV_PLL_DW10(ch) _PIPE(ch, _CHV_PLL_DW10_CH0, _CHV_PLL_DW10_CH1)
> +
> +#define _CHV_PLL_DW11_BCAST		0xC044
> +#define _CHV_PLL_DW11_CH0		0x8044
> +#define _CHV_PLL_DW11_CH1		0x8064
> +#define CHV_PLL_DW11(ch) _PIPE(ch, _CHV_PLL_DW11_CH0, _CHV_PLL_DW11_CH1)
> +
> +#define _CHV_PLL_DW12_CH0		0x8048
> +#define _CHV_PLL_DW12_CH1		0x8068
> +#define CHV_PLL_DW12(ch) _PIPE(ch, _CHV_PLL_DW12_CH0, _CHV_PLL_DW12_CH1)
> +
> +#define _CHV_PLL_DW13_CH0		0x804C
> +#define _CHV_PLL_DW13_CH1		0x806C
> +#define CHV_PLL_DW13(ch) _PIPE(ch, _CHV_PLL_DW13_CH0, _CHV_PLL_DW13_CH1)

DW10-DW13 are unused as well

> +
>  #define _CHV_CMN_DW5_CH0               0x8114
>  #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
>  #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c362d11e..fb27faf 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6576,9 +6576,9 @@ static void chv_update_pll(struct intel_crtc *crtc)
>  	int pipe = crtc->pipe;
>  	int dpll_reg = DPLL(crtc->pipe);
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> -	u32 loopfilter, intcoeff;
> +	u32 loopfilter, tribuf_calcntr;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> -	int refclk;
> +	int vco;
>  
>  	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
>  		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> @@ -6595,6 +6595,7 @@ static void chv_update_pll(struct intel_crtc *crtc)
>  	bestm2 = crtc->config.dpll.m2 >> 22;
>  	bestp1 = crtc->config.dpll.p1;
>  	bestp2 = crtc->config.dpll.p2;
> +	vco = crtc->config.dpll.vco;
>  
>  	/*
>  	 * Enable Refclk and SSC
> @@ -6619,31 +6620,59 @@ static void chv_update_pll(struct intel_crtc *crtc)
>  			DPIO_CHV_M1_DIV_BY_2 |
>  			1 << DPIO_CHV_N_DIV_SHIFT);
>  
> -	/* M2 fraction division */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> +	if (bestm2_frac) {
> +		/* M2 fraction division */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> +
> +		/* M2 fraction division enable */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) &

s/&/|/

As a general style issue I don't like hiding the vlv_dpio_read() inside
the vlv_dpio_write(). So the patter has been:

val = vlv_dpio_read();
change val
vlv_dpip_write(val);

Eventually I'm planning to get rid of the RMW stuff. But I've not done
that yet since I was worried some of the unchanged reset values would
still change as the hardware evolves. I'm hoping stuff has been more or
less nailed down by now so we could probably attempt this.

> +				DPIO_CHV_FRAC_DIV_EN);
> +
> +		/* Program digital lock detect threshold */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)) |
> +				(0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT));
> +	} else {
> +		/* M2 fraction division disable */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) &
> +				~(DPIO_CHV_FRAC_DIV_EN));
>  
> -	/* M2 fraction division enable */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> -		       DPIO_CHV_FRAC_DIV_EN |
> -		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
> +		/* Program digital lock detect threshold */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)) |
> +				(0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT) |
> +				DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
> +	}
>  
>  	/* Loop filter */
> -	refclk = i9xx_get_refclk(&crtc->base, 0);
> -	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
> -		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
> -	if (refclk == 100000)
> -		intcoeff = 11;
> -	else if (refclk == 38400)
> -		intcoeff = 10;
> +	if (vco == 540000)
> +		loopfilter = 0x10803;
> +	else if (vco <= 620000)
> +		loopfilter = 0x30B05;
> +	else if (vco <= 648000)

Those vco limits look way too low. The vco freq should be somewhere
in the 4-6 GHz range. Are these off by a factor of 10, or were you
thinking of some other clock here?

> +		loopfilter = 0x30904;
> +	else
> +		loopfilter = 0x10803;

I'd like to have names for all the magic bits, especially as the spec
situation is what it is, so decoding magic numbers is a bit painful.

> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port),
> +			((vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW6(port)) &
> +			0xFF000000) | loopfilter));

The top bits seem to be all reserved and default to 0. So the mask and
RMW can surely go?

> +
> +	if (vco <= 620000)
> +		tribuf_calcntr = 0x9;
> +	else if (vco <= 648000)
> +		tribuf_calcntr = 0x8;
>  	else
> -		intcoeff = 9;
> -	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
> +		tribuf_calcntr = 0;
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port),
> +			((vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)) &
> +			0xFFFFFF00) | tribuf_calcntr));
>  
>  	/* AFC Recal */
>  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
>  			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> -			DPIO_AFC_RECAL);
> +			DPIO_AFC_RECAL | DPIO_DCLKP_EN);

Why this? We enable it in chv_enable_pll() already after the PLL itself
has been enabled. Is that too late for some reason?


Generally I think the patch should be split into several parts:
- frac vs. int divider
- int_lock_threshold
- loop filter stuff
- dclkp enable, if really needed, and the commit message should say why
  it's needed.


On a slightly related topic, yesterday I managed to narrow down some kind
of problem with data lane DCC calibration. It manifests as link training
failing when driving DP port B with pipe A after the cmnlane power well
has been turned off, or if port B has been driven with pipe B previously.
If I retry the modeset a second time the link training will succeed. I
also managed to make it work by forcing a DCC calibration in
chv_pre_enable_dp(). What's slightly odd is that with pipe A the forced
calibration succeeds, but with pipe B it doesn't and yet pipe B always
works and the calibration status seems to indicates success after the
DP port register has been enabled. I'm still looking into this, but I
was just wondering if you've seen anything similar?

>  
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
> -- 
> 1.7.9.5

-- 
Ville Syrjälä
Intel OTC
---------------------------------------------------------------------
Intel Finland Oy
Registered Address: PL 281, 00181 Helsinki 
Business Identity Code: 0357606 - 4 
Domiciled in Helsinki 

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: More DPIO magic for CHV HDMI & DP

[Jani Nikula]

On Thu, 29 Jan 2015, Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> wrote:
> This patch implements latest changes in Gain, lock threshold and integer
> co-efficient values using sideband r/w. Without these changes there will
> be signal integrity issues for both HDMI and DP.

Vijay, are you planning on sending a v2 of the patch? I'd like to see if
it helps with bugs

https://bugs.freedesktop.org/show_bug.cgi?id=83870
https://bugs.freedesktop.org/show_bug.cgi?id=84304

BR,
Jani.

>
> Change-Id: I7b7151b5ab3a52c4c912cf10602c69a7d1a70222
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> Tested-by: Hong Liu <hong.liu@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |   31 ++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |   67 ++++++++++++++++++++++++----------
>  2 files changed, 79 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 137c5e0..2b3f065 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1049,6 +1049,37 @@ enum punit_power_well {
>  #define   DPIO_CHV_PROP_COEFF_SHIFT	0
>  #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
>  
> +#define _CHV_PLL_DW7_CH0		0x801c
> +#define _CHV_PLL_DW7_CH1		0x803c
> +#define CHV_PLL_DW7(ch) _PIPE(ch, _CHV_PLL_DW7_CH0, _CHV_PLL_DW7_CH1)
> +
> +#define _CHV_PLL_DW8_CH0		0x8020
> +#define _CHV_PLL_DW8_CH1		0x81A0
> +#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
> +
> +#define _CHV_PLL_DW9_CH0		0x8024
> +#define _CHV_PLL_DW9_CH1		0x81A4
> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
> +#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
> +
> +#define _CHV_PLL_DW10_CH0		0x8040
> +#define _CHV_PLL_DW10_CH1		0x8060
> +#define CHV_PLL_DW10(ch) _PIPE(ch, _CHV_PLL_DW10_CH0, _CHV_PLL_DW10_CH1)
> +
> +#define _CHV_PLL_DW11_BCAST		0xC044
> +#define _CHV_PLL_DW11_CH0		0x8044
> +#define _CHV_PLL_DW11_CH1		0x8064
> +#define CHV_PLL_DW11(ch) _PIPE(ch, _CHV_PLL_DW11_CH0, _CHV_PLL_DW11_CH1)
> +
> +#define _CHV_PLL_DW12_CH0		0x8048
> +#define _CHV_PLL_DW12_CH1		0x8068
> +#define CHV_PLL_DW12(ch) _PIPE(ch, _CHV_PLL_DW12_CH0, _CHV_PLL_DW12_CH1)
> +
> +#define _CHV_PLL_DW13_CH0		0x804C
> +#define _CHV_PLL_DW13_CH1		0x806C
> +#define CHV_PLL_DW13(ch) _PIPE(ch, _CHV_PLL_DW13_CH0, _CHV_PLL_DW13_CH1)
> +
>  #define _CHV_CMN_DW5_CH0               0x8114
>  #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
>  #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c362d11e..fb27faf 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6576,9 +6576,9 @@ static void chv_update_pll(struct intel_crtc *crtc)
>  	int pipe = crtc->pipe;
>  	int dpll_reg = DPLL(crtc->pipe);
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> -	u32 loopfilter, intcoeff;
> +	u32 loopfilter, tribuf_calcntr;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> -	int refclk;
> +	int vco;
>  
>  	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
>  		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
> @@ -6595,6 +6595,7 @@ static void chv_update_pll(struct intel_crtc *crtc)
>  	bestm2 = crtc->config.dpll.m2 >> 22;
>  	bestp1 = crtc->config.dpll.p1;
>  	bestp2 = crtc->config.dpll.p2;
> +	vco = crtc->config.dpll.vco;
>  
>  	/*
>  	 * Enable Refclk and SSC
> @@ -6619,31 +6620,59 @@ static void chv_update_pll(struct intel_crtc *crtc)
>  			DPIO_CHV_M1_DIV_BY_2 |
>  			1 << DPIO_CHV_N_DIV_SHIFT);
>  
> -	/* M2 fraction division */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> +	if (bestm2_frac) {
> +		/* M2 fraction division */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> +
> +		/* M2 fraction division enable */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) &
> +				DPIO_CHV_FRAC_DIV_EN);
> +
> +		/* Program digital lock detect threshold */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)) |
> +				(0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT));
> +	} else {
> +		/* M2 fraction division disable */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) &
> +				~(DPIO_CHV_FRAC_DIV_EN));
>  
> -	/* M2 fraction division enable */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> -		       DPIO_CHV_FRAC_DIV_EN |
> -		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
> +		/* Program digital lock detect threshold */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)) |
> +				(0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT) |
> +				DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
> +	}
>  
>  	/* Loop filter */
> -	refclk = i9xx_get_refclk(&crtc->base, 0);
> -	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
> -		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
> -	if (refclk == 100000)
> -		intcoeff = 11;
> -	else if (refclk == 38400)
> -		intcoeff = 10;
> +	if (vco == 540000)
> +		loopfilter = 0x10803;
> +	else if (vco <= 620000)
> +		loopfilter = 0x30B05;
> +	else if (vco <= 648000)
> +		loopfilter = 0x30904;
> +	else
> +		loopfilter = 0x10803;
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port),
> +			((vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW6(port)) &
> +			0xFF000000) | loopfilter));
> +
> +	if (vco <= 620000)
> +		tribuf_calcntr = 0x9;
> +	else if (vco <= 648000)
> +		tribuf_calcntr = 0x8;
>  	else
> -		intcoeff = 9;
> -	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
> +		tribuf_calcntr = 0;
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port),
> +			((vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)) &
> +			0xFFFFFF00) | tribuf_calcntr));
>  
>  	/* AFC Recal */
>  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
>  			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> -			DPIO_AFC_RECAL);
> +			DPIO_AFC_RECAL | DPIO_DCLKP_EN);
>  
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: More DPIO magic for CHV HDMI & DP

[Purushothaman, Vijay A]

On 1/30/2015 4:39 PM, Ville Syrjälä wrote:
> On Fri, Jan 30, 2015 at 12:01:53AM +0530, Vijay Purushothaman wrote:
>> This patch implements latest changes in Gain, lock threshold and integer
>> co-efficient values using sideband r/w. Without these changes there will
>> be signal integrity issues for both HDMI and DP.
>>
>> Change-Id: I7b7151b5ab3a52c4c912cf10602c69a7d1a70222
>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
>> Tested-by: Hong Liu <hong.liu@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h      |   31 ++++++++++++++++
>>   drivers/gpu/drm/i915/intel_display.c |   67 ++++++++++++++++++++++++----------
>>   2 files changed, 79 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 137c5e0..2b3f065 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1049,6 +1049,37 @@ enum punit_power_well {
>>   #define   DPIO_CHV_PROP_COEFF_SHIFT	0
>>   #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
>>   
>> +#define _CHV_PLL_DW7_CH0		0x801c
>> +#define _CHV_PLL_DW7_CH1		0x803c
>> +#define CHV_PLL_DW7(ch) _PIPE(ch, _CHV_PLL_DW7_CH0, _CHV_PLL_DW7_CH1)
> unused
I will remove these definitions in the next patch series.

>
>> +
>> +#define _CHV_PLL_DW8_CH0		0x8020
>> +#define _CHV_PLL_DW8_CH1		0x81A0
>> +#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>> +
>> +#define _CHV_PLL_DW9_CH0		0x8024
>> +#define _CHV_PLL_DW9_CH1		0x81A4
>> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
>> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
>> +#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
>> +
>> +#define _CHV_PLL_DW10_CH0		0x8040
>> +#define _CHV_PLL_DW10_CH1		0x8060
>> +#define CHV_PLL_DW10(ch) _PIPE(ch, _CHV_PLL_DW10_CH0, _CHV_PLL_DW10_CH1)
>> +
>> +#define _CHV_PLL_DW11_BCAST		0xC044
>> +#define _CHV_PLL_DW11_CH0		0x8044
>> +#define _CHV_PLL_DW11_CH1		0x8064
>> +#define CHV_PLL_DW11(ch) _PIPE(ch, _CHV_PLL_DW11_CH0, _CHV_PLL_DW11_CH1)
>> +
>> +#define _CHV_PLL_DW12_CH0		0x8048
>> +#define _CHV_PLL_DW12_CH1		0x8068
>> +#define CHV_PLL_DW12(ch) _PIPE(ch, _CHV_PLL_DW12_CH0, _CHV_PLL_DW12_CH1)
>> +
>> +#define _CHV_PLL_DW13_CH0		0x804C
>> +#define _CHV_PLL_DW13_CH1		0x806C
>> +#define CHV_PLL_DW13(ch) _PIPE(ch, _CHV_PLL_DW13_CH0, _CHV_PLL_DW13_CH1)
> DW10-DW13 are unused as well
I will remove these definitions as well.

>> +
>>   #define _CHV_CMN_DW5_CH0               0x8114
>>   #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
>>   #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index c362d11e..fb27faf 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6576,9 +6576,9 @@ static void chv_update_pll(struct intel_crtc *crtc)
>>   	int pipe = crtc->pipe;
>>   	int dpll_reg = DPLL(crtc->pipe);
>>   	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>> -	u32 loopfilter, intcoeff;
>> +	u32 loopfilter, tribuf_calcntr;
>>   	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>> -	int refclk;
>> +	int vco;
>>   
>>   	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
>>   		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
>> @@ -6595,6 +6595,7 @@ static void chv_update_pll(struct intel_crtc *crtc)
>>   	bestm2 = crtc->config.dpll.m2 >> 22;
>>   	bestp1 = crtc->config.dpll.p1;
>>   	bestp2 = crtc->config.dpll.p2;
>> +	vco = crtc->config.dpll.vco;
>>   
>>   	/*
>>   	 * Enable Refclk and SSC
>> @@ -6619,31 +6620,59 @@ static void chv_update_pll(struct intel_crtc *crtc)
>>   			DPIO_CHV_M1_DIV_BY_2 |
>>   			1 << DPIO_CHV_N_DIV_SHIFT);
>>   
>> -	/* M2 fraction division */
>> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>> +	if (bestm2_frac) {
>> +		/* M2 fraction division */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>> +
>> +		/* M2 fraction division enable */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
>> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) &
> s/&/|/
>
> As a general style issue I don't like hiding the vlv_dpio_read() inside
> the vlv_dpio_write(). So the patter has been:
>
> val = vlv_dpio_read();
> change val
> vlv_dpip_write(val);
>
> Eventually I'm planning to get rid of the RMW stuff. But I've not done
> that yet since I was worried some of the unchanged reset values would
> still change as the hardware evolves. I'm hoping stuff has been more or
> less nailed down by now so we could probably attempt this.
I was trying to follow the same convention used in this function. I do 
agree that hiding vlv_dpio_read() inside vlv_dpio_write() is not a good 
practice.
I would prefer to keep the RMW stuff though. In general i am averse to 
touch anything in DPIO side logic since it results in many trial and 
errors before we get the sequence right.

>
>> +				DPIO_CHV_FRAC_DIV_EN);
>> +
>> +		/* Program digital lock detect threshold */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
>> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)) |
>> +				(0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT));
>> +	} else {
>> +		/* M2 fraction division disable */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
>> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) &
>> +				~(DPIO_CHV_FRAC_DIV_EN));
>>   
>> -	/* M2 fraction division enable */
>> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
>> -		       DPIO_CHV_FRAC_DIV_EN |
>> -		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
>> +		/* Program digital lock detect threshold */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
>> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)) |
>> +				(0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT) |
>> +				DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
>> +	}
>>   
>>   	/* Loop filter */
>> -	refclk = i9xx_get_refclk(&crtc->base, 0);
>> -	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
>> -		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
>> -	if (refclk == 100000)
>> -		intcoeff = 11;
>> -	else if (refclk == 38400)
>> -		intcoeff = 10;
>> +	if (vco == 540000)
>> +		loopfilter = 0x10803;
>> +	else if (vco <= 620000)
>> +		loopfilter = 0x30B05;
>> +	else if (vco <= 648000)
> Those vco limits look way too low. The vco freq should be somewhere
> in the 4-6 GHz range. Are these off by a factor of 10, or were you
> thinking of some other clock here?
The values used are in KHz range. I will fix this in a proper way in 
next patch series.
>
>> +		loopfilter = 0x30904;
>> +	else
>> +		loopfilter = 0x10803;
> I'd like to have names for all the magic bits, especially as the spec
> situation is what it is, so decoding magic numbers is a bit painful.
Will try my level best to decode the magic bits. This value is used 
as-is from windows code snippet. I was told that the PHY h/w team passed 
these magic numbers in the same format and since it was working in 
windows, my request for detailed documentation is not getting the right 
attention.

>
>> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port),
>> +			((vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW6(port)) &
>> +			0xFF000000) | loopfilter));
> The top bits seem to be all reserved and default to 0. So the mask and
> RMW can surely go?
Yes.

>
>> +
>> +	if (vco <= 620000)
>> +		tribuf_calcntr = 0x9;
>> +	else if (vco <= 648000)
>> +		tribuf_calcntr = 0x8;
>>   	else
>> -		intcoeff = 9;
>> -	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
>> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
>> +		tribuf_calcntr = 0;
>> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port),
>> +			((vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)) &
>> +			0xFFFFFF00) | tribuf_calcntr));
>>   
>>   	/* AFC Recal */
>>   	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
>>   			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
>> -			DPIO_AFC_RECAL);
>> +			DPIO_AFC_RECAL | DPIO_DCLKP_EN);
> Why this? We enable it in chv_enable_pll() already after the PLL itself
> has been enabled. Is that too late for some reason?
Again this is based on trial and error in other OS and the tip from 
windows driver team is to set both DPIO_AFC_RECAL and DPIO_CLKP_EN in a 
single shot. Otherwise they are seeing some stability issues. I guess i 
will have to move this part to chv_enable_pll.
>
>
> Generally I think the patch should be split into several parts:
> - frac vs. int divider
> - int_lock_threshold
> - loop filter stuff
> - dclkp enable, if really needed, and the commit message should say why
>    it's needed.
sure. I will address this in my next patch set.
>
> On a slightly related topic, yesterday I managed to narrow down some kind
> of problem with data lane DCC calibration. It manifests as link training
> failing when driving DP port B with pipe A after the cmnlane power well
> has been turned off, or if port B has been driven with pipe B previously.
> If I retry the modeset a second time the link training will succeed. I
> also managed to make it work by forcing a DCC calibration in
> chv_pre_enable_dp(). What's slightly odd is that with pipe A the forced
> calibration succeeds, but with pipe B it doesn't and yet pipe B always
> works and the calibration status seems to indicates success after the
> DP port register has been enabled. I'm still looking into this, but I
> was just wondering if you've seen anything similar?
I have not observed this yet. This could be because  most of our efforts 
are on a different code base - ADF.

Thanks,
Vijay
>
>>   
>>   	mutex_unlock(&dev_priv->dpio_lock);
>>   }
>> -- 
>> 1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: More DPIO magic for CHV HDMI & DP

[Purushothaman, Vijay A]

On 2/10/2015 6:13 PM, Jani Nikula wrote:
> On Thu, 29 Jan 2015, Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> wrote:
>> This patch implements latest changes in Gain, lock threshold and integer
>> co-efficient values using sideband r/w. Without these changes there will
>> be signal integrity issues for both HDMI and DP.
> Vijay, are you planning on sending a v2 of the patch? I'd like to see if
> it helps with bugs
>
> https://bugs.freedesktop.org/show_bug.cgi?id=83870
> https://bugs.freedesktop.org/show_bug.cgi?id=84304
I will post the next patch series tomorrow. But i don't have a working 
CHV setup. I might need some help to test those patches.

Thanks,
Vijay

>
> BR,
> Jani.
>
>> Change-Id: I7b7151b5ab3a52c4c912cf10602c69a7d1a70222
>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
>> Tested-by: Hong Liu <hong.liu@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h      |   31 ++++++++++++++++
>>   drivers/gpu/drm/i915/intel_display.c |   67 ++++++++++++++++++++++++----------
>>   2 files changed, 79 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 137c5e0..2b3f065 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1049,6 +1049,37 @@ enum punit_power_well {
>>   #define   DPIO_CHV_PROP_COEFF_SHIFT	0
>>   #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
>>   
>> +#define _CHV_PLL_DW7_CH0		0x801c
>> +#define _CHV_PLL_DW7_CH1		0x803c
>> +#define CHV_PLL_DW7(ch) _PIPE(ch, _CHV_PLL_DW7_CH0, _CHV_PLL_DW7_CH1)
>> +
>> +#define _CHV_PLL_DW8_CH0		0x8020
>> +#define _CHV_PLL_DW8_CH1		0x81A0
>> +#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>> +
>> +#define _CHV_PLL_DW9_CH0		0x8024
>> +#define _CHV_PLL_DW9_CH1		0x81A4
>> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
>> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
>> +#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
>> +
>> +#define _CHV_PLL_DW10_CH0		0x8040
>> +#define _CHV_PLL_DW10_CH1		0x8060
>> +#define CHV_PLL_DW10(ch) _PIPE(ch, _CHV_PLL_DW10_CH0, _CHV_PLL_DW10_CH1)
>> +
>> +#define _CHV_PLL_DW11_BCAST		0xC044
>> +#define _CHV_PLL_DW11_CH0		0x8044
>> +#define _CHV_PLL_DW11_CH1		0x8064
>> +#define CHV_PLL_DW11(ch) _PIPE(ch, _CHV_PLL_DW11_CH0, _CHV_PLL_DW11_CH1)
>> +
>> +#define _CHV_PLL_DW12_CH0		0x8048
>> +#define _CHV_PLL_DW12_CH1		0x8068
>> +#define CHV_PLL_DW12(ch) _PIPE(ch, _CHV_PLL_DW12_CH0, _CHV_PLL_DW12_CH1)
>> +
>> +#define _CHV_PLL_DW13_CH0		0x804C
>> +#define _CHV_PLL_DW13_CH1		0x806C
>> +#define CHV_PLL_DW13(ch) _PIPE(ch, _CHV_PLL_DW13_CH0, _CHV_PLL_DW13_CH1)
>> +
>>   #define _CHV_CMN_DW5_CH0               0x8114
>>   #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
>>   #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index c362d11e..fb27faf 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6576,9 +6576,9 @@ static void chv_update_pll(struct intel_crtc *crtc)
>>   	int pipe = crtc->pipe;
>>   	int dpll_reg = DPLL(crtc->pipe);
>>   	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>> -	u32 loopfilter, intcoeff;
>> +	u32 loopfilter, tribuf_calcntr;
>>   	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>> -	int refclk;
>> +	int vco;
>>   
>>   	crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
>>   		DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
>> @@ -6595,6 +6595,7 @@ static void chv_update_pll(struct intel_crtc *crtc)
>>   	bestm2 = crtc->config.dpll.m2 >> 22;
>>   	bestp1 = crtc->config.dpll.p1;
>>   	bestp2 = crtc->config.dpll.p2;
>> +	vco = crtc->config.dpll.vco;
>>   
>>   	/*
>>   	 * Enable Refclk and SSC
>> @@ -6619,31 +6620,59 @@ static void chv_update_pll(struct intel_crtc *crtc)
>>   			DPIO_CHV_M1_DIV_BY_2 |
>>   			1 << DPIO_CHV_N_DIV_SHIFT);
>>   
>> -	/* M2 fraction division */
>> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>> +	if (bestm2_frac) {
>> +		/* M2 fraction division */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>> +
>> +		/* M2 fraction division enable */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
>> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) &
>> +				DPIO_CHV_FRAC_DIV_EN);
>> +
>> +		/* Program digital lock detect threshold */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
>> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)) |
>> +				(0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT));
>> +	} else {
>> +		/* M2 fraction division disable */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
>> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)) &
>> +				~(DPIO_CHV_FRAC_DIV_EN));
>>   
>> -	/* M2 fraction division enable */
>> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
>> -		       DPIO_CHV_FRAC_DIV_EN |
>> -		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
>> +		/* Program digital lock detect threshold */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port),
>> +				vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)) |
>> +				(0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT) |
>> +				DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
>> +	}
>>   
>>   	/* Loop filter */
>> -	refclk = i9xx_get_refclk(&crtc->base, 0);
>> -	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
>> -		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
>> -	if (refclk == 100000)
>> -		intcoeff = 11;
>> -	else if (refclk == 38400)
>> -		intcoeff = 10;
>> +	if (vco == 540000)
>> +		loopfilter = 0x10803;
>> +	else if (vco <= 620000)
>> +		loopfilter = 0x30B05;
>> +	else if (vco <= 648000)
>> +		loopfilter = 0x30904;
>> +	else
>> +		loopfilter = 0x10803;
>> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port),
>> +			((vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW6(port)) &
>> +			0xFF000000) | loopfilter));
>> +
>> +	if (vco <= 620000)
>> +		tribuf_calcntr = 0x9;
>> +	else if (vco <= 648000)
>> +		tribuf_calcntr = 0x8;
>>   	else
>> -		intcoeff = 9;
>> -	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
>> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
>> +		tribuf_calcntr = 0;
>> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port),
>> +			((vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)) &
>> +			0xFFFFFF00) | tribuf_calcntr));
>>   
>>   	/* AFC Recal */
>>   	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
>>   			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
>> -			DPIO_AFC_RECAL);
>> +			DPIO_AFC_RECAL | DPIO_DCLKP_EN);
>>   
>>   	mutex_unlock(&dev_priv->dpio_lock);
>>   }
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v2 0/5] More DPIO magic for CHV HDMI & DP

[Vijay Purushothaman]

Changes since version 1:
	Addressed Ville's review comments
	Decoded the magic numbers as much as possible
	Split the single patch into logical patch set 
	Dropped the DPIO_CLK_EN changes


Vijay Purushothaman (5):
  drm/i915: Add new PHY reg definitions for lock threshold
  drm/i915: Limit max VCO supported in CHV to 6.48GHz
  drm/i915: Disable M2 frac division for integer case
  drm/i915: Initialize CHV digital lock detect threshold
  drm/i915: Update prop, int co-eff and gain threshold for CHV

 drivers/gpu/drm/i915/i915_reg.h      |   11 +++++
 drivers/gpu/drm/i915/intel_display.c |   78 +++++++++++++++++++++++++---------
 2 files changed, 70 insertions(+), 19 deletions(-)

-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v2 1/5] drm/i915: Add new PHY reg definitions for lock threshold

[Vijay Purushothaman]

Added new PHY register definitions to control TDC buffer calibration and
digital lock threshold.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc91de..5814f67 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1025,6 +1025,16 @@ enum skl_disp_power_wells {
 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
 
+#define _CHV_PLL_DW8_CH0		0x8020
+#define _CHV_PLL_DW8_CH1		0x81A0
+#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
+
+#define _CHV_PLL_DW9_CH0		0x8024
+#define _CHV_PLL_DW9_CH1		0x81A4
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
+#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
+
 #define _CHV_CMN_DW5_CH0               0x8114
 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
 #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz

[Vijay Purushothaman]

As per the recommendation from PHY team, limit the max vco supported in CHV to 6.48 GHz

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b0fe9f..4e710f6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
 	 * them would make no difference.
 	 */
 	.dot = { .min = 25000 * 5, .max = 540000 * 5},
-	.vco = { .min = 4860000, .max = 6700000 },
+	.vco = { .min = 4860000, .max = 6480000 },
 	.n = { .min = 1, .max = 1 },
 	.m1 = { .min = 2, .max = 2 },
 	.m2 = { .min = 24 << 22, .max = 175 << 22 },
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v2 3/5] drm/i915: Disable M2 frac division for integer case

[Vijay Purushothaman]

Handle M2 frac division for both M2 frac and int cases

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4e710f6..87d1721 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6041,6 +6041,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
 	u32 loopfilter, intcoeff;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+	u32 dpio_val;
 	int refclk;
 
 	bestn = pipe_config->dpll.n;
@@ -6049,6 +6050,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	bestm2 = pipe_config->dpll.m2 >> 22;
 	bestp1 = pipe_config->dpll.p1;
 	bestp2 = pipe_config->dpll.p2;
+	dpio_val = 0;
 
 	/*
 	 * Enable Refclk and SSC
@@ -6073,13 +6075,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 			DPIO_CHV_M1_DIV_BY_2 |
 			1 << DPIO_CHV_N_DIV_SHIFT);
 
-	/* M2 fraction division */
-	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+	if (bestm2_frac) {
+		/* M2 fraction division */
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
 
-	/* M2 fraction division enable */
-	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
-		       DPIO_CHV_FRAC_DIV_EN |
-		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+		/* M2 fraction division enable */
+		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+		dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+	} else {
+		/* M2 fraction division disable */
+		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+		dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+	}
 
 	/* Loop filter */
 	refclk = i9xx_get_refclk(crtc, 0);
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v2 4/5] drm/i915: Initialize CHV digital lock detect threshold

[Vijay Purushothaman]

Initialize lock detect threshold and select coarse threshold if M2 is
zero

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 87d1721..ae2a77f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6085,11 +6085,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 		dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
 		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
 
+		/* Program digital lock detect threshold */
+		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+		dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
 	} else {
 		/* M2 fraction division disable */
 		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
 		dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
 		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+		/* Program digital lock detect threshold */
+		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+		dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
 	}
 
 	/* Loop filter */
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV

[Vijay Purushothaman]

This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |   42 ++++++++++++++++++++++++----------
 2 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5814f67..b5bce4e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1027,6 +1027,7 @@ enum skl_disp_power_wells {
 
 #define _CHV_PLL_DW8_CH0		0x8020
 #define _CHV_PLL_DW8_CH1		0x81A0
+#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
 
 #define _CHV_PLL_DW9_CH0		0x8024
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ae2a77f..ca02cf7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6039,10 +6039,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	int pipe = crtc->pipe;
 	int dpll_reg = DPLL(crtc->pipe);
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
-	u32 loopfilter, intcoeff;
+	u32 loopfilter, tribuf_calcntr;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
 	u32 dpio_val;
-	int refclk;
+	int vco;
 
 	bestn = pipe_config->dpll.n;
 	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
@@ -6050,7 +6050,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	bestm2 = pipe_config->dpll.m2 >> 22;
 	bestp1 = pipe_config->dpll.p1;
 	bestp2 = pipe_config->dpll.p2;
+	vco = pipe_config->dpll.vco;
 	dpio_val = 0;
+	loopfilter = 0;
 
 	/*
 	 * Enable Refclk and SSC
@@ -6104,18 +6106,34 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	}
 
 	/* Loop filter */
-	refclk = i9xx_get_refclk(crtc, 0);
-	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
-		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
-	if (refclk == 100000)
-		intcoeff = 11;
-	else if (refclk == 38400)
-		intcoeff = 10;
-	else
-		intcoeff = 9;
-	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+	if (vco == 5400000) {
+		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0;
+	} else if (vco <= 6200000) {
+		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0x9;
+	} else if (vco <= 6480000) {
+		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0x8;
+	} else {
+		/* Not supported. Apply the same limits as in the max case */
+		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0;
+	}
 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
 
+	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
 	/* AFC Recal */
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
 			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 1/5] drm/i915: Add new PHY reg definitions for lock threshold

[Ville Syrjälä]

On Mon, Feb 16, 2015 at 03:07:58PM +0530, Vijay Purushothaman wrote:
> Added new PHY register definitions to control TDC buffer calibration and
> digital lock threshold.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h |   10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1dc91de..5814f67 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1025,6 +1025,16 @@ enum skl_disp_power_wells {
>  #define   DPIO_CHV_PROP_COEFF_SHIFT	0
>  #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
>  
> +#define _CHV_PLL_DW8_CH0		0x8020
> +#define _CHV_PLL_DW8_CH1		0x81A0
> +#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
> +
> +#define _CHV_PLL_DW9_CH0		0x8024
> +#define _CHV_PLL_DW9_CH1		0x81A4
> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
> +#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
> +
>  #define _CHV_CMN_DW5_CH0               0x8114
>  #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
>  #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz

[Ville Syrjälä]

On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
> As per the recommendation from PHY team, limit the max vco supported in CHV to 6.48 GHz
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3b0fe9f..4e710f6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
>  	 * them would make no difference.
>  	 */
>  	.dot = { .min = 25000 * 5, .max = 540000 * 5},
> -	.vco = { .min = 4860000, .max = 6700000 },
> +	.vco = { .min = 4860000, .max = 6480000 },

I have a patch here to reduce the minimum to 4.80 GHz, otherwise I can't
get my 2560x1440 HDMI display working (241.5 MHz clock). With that change
we still have a gap (233-240 MHz) in the frequencies we can produce.
Reducing the max to 6.48 GHz will increase that gap to 216-240 MHz, which
is a bit unfortunate. But if that's the recommendation we should follow
it I suppose, and hope no HDMI displays will want such frequencies.

Is there an updated spreadsheet available with the new limits? Quite a
few of the frequencies in the original spreadsheet did have vco>6.48
GHz.

I any case this seems OK, so
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  	.n = { .min = 1, .max = 1 },
>  	.m1 = { .min = 2, .max = 2 },
>  	.m2 = { .min = 24 << 22, .max = 175 << 22 },
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 3/5] drm/i915: Disable M2 frac division for integer case

[Ville Syrjälä]

On Mon, Feb 16, 2015 at 03:08:00PM +0530, Vijay Purushothaman wrote:
> Handle M2 frac division for both M2 frac and int cases
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   23 +++++++++++++++++------
>  1 file changed, 17 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4e710f6..87d1721 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6041,6 +6041,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>  	u32 loopfilter, intcoeff;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> +	u32 dpio_val;
>  	int refclk;
>  
>  	bestn = pipe_config->dpll.n;
> @@ -6049,6 +6050,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	bestm2 = pipe_config->dpll.m2 >> 22;
>  	bestp1 = pipe_config->dpll.p1;
>  	bestp2 = pipe_config->dpll.p2;
> +	dpio_val = 0;
>  
>  	/*
>  	 * Enable Refclk and SSC
> @@ -6073,13 +6075,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  			DPIO_CHV_M1_DIV_BY_2 |
>  			1 << DPIO_CHV_N_DIV_SHIFT);
>  
> -	/* M2 fraction division */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> +	if (bestm2_frac) {
> +		/* M2 fraction division */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>  
> -	/* M2 fraction division enable */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> -		       DPIO_CHV_FRAC_DIV_EN |
> -		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
> +		/* M2 fraction division enable */
> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> +		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
> +		dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);

Will need to mask out the bits first if you want to use RMW.

> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> +
> +	} else {
> +		/* M2 fraction division disable */
> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> +		dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);

Useless parens.

> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> +	}
>  
>  	/* Loop filter */
>  	refclk = i9xx_get_refclk(crtc, 0);
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 4/5] drm/i915: Initialize CHV digital lock detect threshold

[Ville Syrjälä]

On Mon, Feb 16, 2015 at 03:08:01PM +0530, Vijay Purushothaman wrote:
> Initialize lock detect threshold and select coarse threshold if M2 is
> zero

"if M2 fractional part is zero"?

> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 87d1721..ae2a77f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6085,11 +6085,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  		dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
>  		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
>  
> +		/* Program digital lock detect threshold */
> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
> +		dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);

Again need to clear out the old bits first.

> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
> +
>  	} else {
>  		/* M2 fraction division disable */
>  		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
>  		dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN);
>  		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> +
> +		/* Program digital lock detect threshold */
> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
> +		dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);

Ditto.

> +		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
>  	}
>  
>  	/* Loop filter */
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV

[Ville Syrjälä]

On Mon, Feb 16, 2015 at 03:08:02PM +0530, Vijay Purushothaman wrote:
> This patch implements latest PHY changes in Gain, prop and int co-efficients
> based on the vco freq.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    1 +
>  drivers/gpu/drm/i915/intel_display.c |   42 ++++++++++++++++++++++++----------
>  2 files changed, 31 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5814f67..b5bce4e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1027,6 +1027,7 @@ enum skl_disp_power_wells {
>  
>  #define _CHV_PLL_DW8_CH0		0x8020
>  #define _CHV_PLL_DW8_CH1		0x81A0
> +#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
>  #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>  
>  #define _CHV_PLL_DW9_CH0		0x8024
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ae2a77f..ca02cf7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6039,10 +6039,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	int pipe = crtc->pipe;
>  	int dpll_reg = DPLL(crtc->pipe);
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> -	u32 loopfilter, intcoeff;
> +	u32 loopfilter, tribuf_calcntr;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>  	u32 dpio_val;
> -	int refclk;
> +	int vco;
>  
>  	bestn = pipe_config->dpll.n;
>  	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
> @@ -6050,7 +6050,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	bestm2 = pipe_config->dpll.m2 >> 22;
>  	bestp1 = pipe_config->dpll.p1;
>  	bestp2 = pipe_config->dpll.p2;
> +	vco = pipe_config->dpll.vco;
>  	dpio_val = 0;
> +	loopfilter = 0;
>  
>  	/*
>  	 * Enable Refclk and SSC
> @@ -6104,18 +6106,34 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	}
>  
>  	/* Loop filter */
> -	refclk = i9xx_get_refclk(crtc, 0);
> -	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
> -		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
> -	if (refclk == 100000)
> -		intcoeff = 11;
> -	else if (refclk == 38400)
> -		intcoeff = 10;
> -	else
> -		intcoeff = 9;
> -	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
> +	if (vco == 5400000) {
> +		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0;

In your original patch tribuf_calcntr was 9 here. Which is correct?

> +	} else if (vco <= 6200000) {
> +		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0x9;
> +	} else if (vco <= 6480000) {
> +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0x8;
> +	} else {
> +		/* Not supported. Apply the same limits as in the max case */
> +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);

These too were different in your original patch, but I guess it doens't
matter either way that much since we should never get here.

> +		tribuf_calcntr = 0;
> +	}
>  	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
>  
> +	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
> +	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);

Need to clear out the old bits again. Seems to be 10bits by the looks of it.

> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
> +
>  	/* AFC Recal */
>  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
>  			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz

[Daniel Vetter]

On Mon, Feb 16, 2015 at 01:21:34PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
> > As per the recommendation from PHY team, limit the max vco supported in CHV to 6.48 GHz
> > 
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |    2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 3b0fe9f..4e710f6 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
> >  	 * them would make no difference.
> >  	 */
> >  	.dot = { .min = 25000 * 5, .max = 540000 * 5},
> > -	.vco = { .min = 4860000, .max = 6700000 },
> > +	.vco = { .min = 4860000, .max = 6480000 },
> 
> I have a patch here to reduce the minimum to 4.80 GHz, otherwise I can't
> get my 2560x1440 HDMI display working (241.5 MHz clock). With that change
> we still have a gap (233-240 MHz) in the frequencies we can produce.
> Reducing the max to 6.48 GHz will increase that gap to 216-240 MHz, which
> is a bit unfortunate. But if that's the recommendation we should follow
> it I suppose, and hope no HDMI displays will want such frequencies.
> 
> Is there an updated spreadsheet available with the new limits? Quite a
> few of the frequencies in the original spreadsheet did have vco>6.48
> GHz.

Has the updated doc been dug up meanwhile? A big part of review is getting
access to docs and making sure they're up-to-date too ...
-Daniel

> 
> I any case this seems OK, so
> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> >  	.n = { .min = 1, .max = 1 },
> >  	.m1 = { .min = 2, .max = 2 },
> >  	.m2 = { .min = 24 << 22, .max = 175 << 22 },
> > -- 
> > 1.7.9.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 0/5] More DPIO magic for CHV HDMI & DP

[Daniel Vetter]

On Mon, Feb 16, 2015 at 03:07:57PM +0530, Vijay Purushothaman wrote:
> Changes since version 1:
> 	Addressed Ville's review comments
> 	Decoded the magic numbers as much as possible
> 	Split the single patch into logical patch set 
> 	Dropped the DPIO_CLK_EN changes
> 
> 
> Vijay Purushothaman (5):
>   drm/i915: Add new PHY reg definitions for lock threshold
>   drm/i915: Limit max VCO supported in CHV to 6.48GHz
>   drm/i915: Disable M2 frac division for integer case
>   drm/i915: Initialize CHV digital lock detect threshold
>   drm/i915: Update prop, int co-eff and gain threshold for CHV

Merged the first two patches from this series to dinq, thanks.
-Daniel

> 
>  drivers/gpu/drm/i915/i915_reg.h      |   11 +++++
>  drivers/gpu/drm/i915/intel_display.c |   78 +++++++++++++++++++++++++---------
>  2 files changed, 70 insertions(+), 19 deletions(-)
> 
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz

[Purushothaman, Vijay A]

On 2/23/2015 9:43 PM, Daniel Vetter wrote:
> On Mon, Feb 16, 2015 at 01:21:34PM +0200, Ville Syrjälä wrote:
>> On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
>>> As per the recommendation from PHY team, limit the max vco supported in CHV to 6.48 GHz
>>>
>>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_display.c |    2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>> index 3b0fe9f..4e710f6 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
>>>   	 * them would make no difference.
>>>   	 */
>>>   	.dot = { .min = 25000 * 5, .max = 540000 * 5},
>>> -	.vco = { .min = 4860000, .max = 6700000 },
>>> +	.vco = { .min = 4860000, .max = 6480000 },
>> I have a patch here to reduce the minimum to 4.80 GHz, otherwise I can't
>> get my 2560x1440 HDMI display working (241.5 MHz clock). With that change
>> we still have a gap (233-240 MHz) in the frequencies we can produce.
>> Reducing the max to 6.48 GHz will increase that gap to 216-240 MHz, which
>> is a bit unfortunate. But if that's the recommendation we should follow
>> it I suppose, and hope no HDMI displays will want such frequencies.
>>
>> Is there an updated spreadsheet available with the new limits? Quite a
>> few of the frequencies in the original spreadsheet did have vco>6.48
>> GHz.
> Has the updated doc been dug up meanwhile? A big part of review is getting
> access to docs and making sure they're up-to-date too ...
> -Daniel
I sent the copy of excel sheet that i am using to both of you in another 
mail. I still end up relying on windows driver folks since they seem to 
be having latest information about PHY.

Thanks,
Vijay
>> I any case this seems OK, so
>> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>>>   	.n = { .min = 1, .max = 1 },
>>>   	.m1 = { .min = 2, .max = 2 },
>>>   	.m2 = { .min = 24 << 22, .max = 175 << 22 },
>>> -- 
>>> 1.7.9.5
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> -- 
>> Ville Syrjälä
>> Intel OTC
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV

[Purushothaman, Vijay A]

On 2/16/2015 5:02 PM, Ville Syrjälä wrote:
> On Mon, Feb 16, 2015 at 03:08:02PM +0530, Vijay Purushothaman wrote:
>> This patch implements latest PHY changes in Gain, prop and int co-efficients
>> based on the vco freq.
>>
>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h      |    1 +
>>   drivers/gpu/drm/i915/intel_display.c |   42 ++++++++++++++++++++++++----------
>>   2 files changed, 31 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 5814f67..b5bce4e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1027,6 +1027,7 @@ enum skl_disp_power_wells {
>>   
>>   #define _CHV_PLL_DW8_CH0		0x8020
>>   #define _CHV_PLL_DW8_CH1		0x81A0
>> +#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
>>   #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>>   
>>   #define _CHV_PLL_DW9_CH0		0x8024
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index ae2a77f..ca02cf7 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6039,10 +6039,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>>   	int pipe = crtc->pipe;
>>   	int dpll_reg = DPLL(crtc->pipe);
>>   	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>> -	u32 loopfilter, intcoeff;
>> +	u32 loopfilter, tribuf_calcntr;
>>   	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>>   	u32 dpio_val;
>> -	int refclk;
>> +	int vco;
>>   
>>   	bestn = pipe_config->dpll.n;
>>   	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
>> @@ -6050,7 +6050,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>>   	bestm2 = pipe_config->dpll.m2 >> 22;
>>   	bestp1 = pipe_config->dpll.p1;
>>   	bestp2 = pipe_config->dpll.p2;
>> +	vco = pipe_config->dpll.vco;
>>   	dpio_val = 0;
>> +	loopfilter = 0;
>>   
>>   	/*
>>   	 * Enable Refclk and SSC
>> @@ -6104,18 +6106,34 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>>   	}
>>   
>>   	/* Loop filter */
>> -	refclk = i9xx_get_refclk(crtc, 0);
>> -	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
>> -		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
>> -	if (refclk == 100000)
>> -		intcoeff = 11;
>> -	else if (refclk == 38400)
>> -		intcoeff = 10;
>> -	else
>> -		intcoeff = 9;
>> -	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
>> +	if (vco == 5400000) {
>> +		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
>> +		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
>> +		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
>> +		tribuf_calcntr = 0;
> In your original patch tribuf_calcntr was 9 here. Which is correct?
9 is correct. Thanks for the catch.
>
>> +	} else if (vco <= 6200000) {
>> +		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
>> +		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
>> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
>> +		tribuf_calcntr = 0x9;
>> +	} else if (vco <= 6480000) {
>> +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
>> +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
>> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
>> +		tribuf_calcntr = 0x8;
>> +	} else {
>> +		/* Not supported. Apply the same limits as in the max case */
>> +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
>> +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
>> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> These too were different in your original patch, but I guess it doens't
> matter either way that much since we should never get here.
Correct. Just for clarity, i wanted to use the max limits.

Thanks,
Vijay
>> +		tribuf_calcntr = 0;
>> +	}
>>   	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
>>   
>> +	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
>> +	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
> Need to clear out the old bits again. Seems to be 10bits by the looks of it.
>
>> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
>> +
>>   	/* AFC Recal */
>>   	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
>>   			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/3] drm/i915: Disable M2 frac division for integer case

[Vijay Purushothaman]

v2 : Handle M2 frac division for both M2 frac and int cases

v3 : Addressed Ville's review comments. Cleared the old bits for RMW

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |   24 ++++++++++++++++++------
 2 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..8200e98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
 #define  DPIO_CHV_FIRST_MOD		(0 << 8)
 #define  DPIO_CHV_SECOND_MOD		(1 << 8)
 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
+#define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
 
 #define _CHV_PLL_DW6_CH0		0x8018
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7298796..15904a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
 	u32 loopfilter, intcoeff;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+	u32 dpio_val;
 	int refclk;
 
 	bestn = pipe_config->dpll.n;
@@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	bestm2 = pipe_config->dpll.m2 >> 22;
 	bestp1 = pipe_config->dpll.p1;
 	bestp2 = pipe_config->dpll.p2;
+	dpio_val = 0;
 
 	/*
 	 * Enable Refclk and SSC
@@ -6163,13 +6165,23 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 			DPIO_CHV_M1_DIV_BY_2 |
 			1 << DPIO_CHV_N_DIV_SHIFT);
 
-	/* M2 fraction division */
-	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+	if (bestm2_frac) {
+		/* M2 fraction division */
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
 
-	/* M2 fraction division enable */
-	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
-		       DPIO_CHV_FRAC_DIV_EN |
-		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+		/* M2 fraction division enable */
+		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+		dpio_val &= ~DPIO_CHV_FEEDFWD_GAIN_MASK;
+		dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+	} else {
+		/* M2 fraction division disable */
+		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+		dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+	}
 
 	/* Loop filter */
 	refclk = i9xx_get_refclk(crtc, 0);
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold

[Vijay Purushothaman]

Initialize lock detect threshold and select coarse threshold for the
case where M2 fraction division is disabled.

v2: Split the changes into multiple smaller patches based on review by
Ville

v3: Addressed rest of the review comments. Clear out the old bits before
we modify those bits as part of RMW

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |   13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200e98..1a0f94e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
 #define _CHV_PLL_DW9_CH0		0x8024
 #define _CHV_PLL_DW9_CH1		0x81A4
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 15904a8..a6b5786 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6176,11 +6176,24 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 		dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
 		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
 
+		/* Program digital lock detect threshold */
+		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+		dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
+		dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
 	} else {
 		/* M2 fraction division disable */
 		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
 		dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
 		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
+
+		/* Program digital lock detect threshold */
+		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+		dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
+		dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
 	}
 
 	/* Loop filter */
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV

[Vijay Purushothaman]

This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.

v2: Split the original changes into multiple smaller patches based on
review by Ville

v3: Addressed Ville's review comments. Fixed the error introduced in v2.
Clear the old bits before we modify those bits as part of RMW.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    2 ++
 drivers/gpu/drm/i915/intel_display.c |   43 ++++++++++++++++++++++++----------
 2 files changed, 33 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a0f94e..5000184 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
 
 #define _CHV_PLL_DW8_CH0		0x8020
 #define _CHV_PLL_DW8_CH1		0x81A0
+#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
+#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0xFF << 0)
 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
 
 #define _CHV_PLL_DW9_CH0		0x8024
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a6b5786..4e08a14 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6129,10 +6129,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	int pipe = crtc->pipe;
 	int dpll_reg = DPLL(crtc->pipe);
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
-	u32 loopfilter, intcoeff;
+	u32 loopfilter, tribuf_calcntr;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
 	u32 dpio_val;
-	int refclk;
+	int vco;
 
 	bestn = pipe_config->dpll.n;
 	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
@@ -6140,7 +6140,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	bestm2 = pipe_config->dpll.m2 >> 22;
 	bestp1 = pipe_config->dpll.p1;
 	bestp2 = pipe_config->dpll.p2;
+	vco = pipe_config->dpll.vco;
 	dpio_val = 0;
+	loopfilter = 0;
 
 	/*
 	 * Enable Refclk and SSC
@@ -6197,18 +6199,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	}
 
 	/* Loop filter */
-	refclk = i9xx_get_refclk(crtc, 0);
-	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
-		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
-	if (refclk == 100000)
-		intcoeff = 11;
-	else if (refclk == 38400)
-		intcoeff = 10;
-	else
-		intcoeff = 9;
-	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+	if (vco == 5400000) {
+		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 9;
+	} else if (vco <= 6200000) {
+		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0x9;
+	} else if (vco <= 6480000) {
+		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0x8;
+	} else {
+		/* Not supported. Apply the same limits as in the max case */
+		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0;
+	}
 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
 
+	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
+	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
 	/* AFC Recal */
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
 			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/3] drm/i915: Disable M2 frac division for integer case

[Ville Syrjälä]

On Tue, Mar 03, 2015 at 08:41:54PM +0530, Vijay Purushothaman wrote:
> v2 : Handle M2 frac division for both M2 frac and int cases
> 
> v3 : Addressed Ville's review comments. Cleared the old bits for RMW
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    1 +
>  drivers/gpu/drm/i915/intel_display.c |   24 ++++++++++++++++++------
>  2 files changed, 19 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 55143cb..8200e98 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
>  #define  DPIO_CHV_FIRST_MOD		(0 << 8)
>  #define  DPIO_CHV_SECOND_MOD		(1 << 8)
>  #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
> +#define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
>  #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
>  
>  #define _CHV_PLL_DW6_CH0		0x8018
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7298796..15904a8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>  	u32 loopfilter, intcoeff;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> +	u32 dpio_val;
>  	int refclk;
>  
>  	bestn = pipe_config->dpll.n;
> @@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	bestm2 = pipe_config->dpll.m2 >> 22;
>  	bestp1 = pipe_config->dpll.p1;
>  	bestp2 = pipe_config->dpll.p2;
> +	dpio_val = 0;
>  
>  	/*
>  	 * Enable Refclk and SSC
> @@ -6163,13 +6165,23 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  			DPIO_CHV_M1_DIV_BY_2 |
>  			1 << DPIO_CHV_N_DIV_SHIFT);
>  
> -	/* M2 fraction division */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> +	if (bestm2_frac) {
> +		/* M2 fraction division */
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>  
> -	/* M2 fraction division enable */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> -		       DPIO_CHV_FRAC_DIV_EN |
> -		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
> +		/* M2 fraction division enable */
> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> +		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
> +		dpio_val &= ~DPIO_CHV_FEEDFWD_GAIN_MASK;
> +		dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> +
> +	} else {
> +		/* M2 fraction division disable */
> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> +		dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);

You're not writing the feedfwd gain here. The register docs list it as
'Feedforwad gain for fractional mode/SSC mode PLL'. The SSC part there
makes me think these bits might mean something even if the fractional
divider is not used.

At least I don't see any harm in setting it even if the fractional
divider is not used. So with that in mind I'd probably write this as
something like:

val = read(PLL_DW3)
val &= ~(FRAC_DIV_EN | FEEDFWD_GAIN_MASK)
val |= 2 << FEEDFWD_GAIN_SHIFT;
if (bestm2_trac)
	val |= FRAC_DIV_EN;
write(PLL_DW3, val);

This should also make it less likely we will accidentally update
only one of the branches in the future when both need changing.

> +	}
>  
>  	/* Loop filter */
>  	refclk = i9xx_get_refclk(crtc, 0);
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold

[Ville Syrjälä]

On Tue, Mar 03, 2015 at 08:43:12PM +0530, Vijay Purushothaman wrote:
> Initialize lock detect threshold and select coarse threshold for the
> case where M2 fraction division is disabled.
> 
> v2: Split the changes into multiple smaller patches based on review by
> Ville
> 
> v3: Addressed rest of the review comments. Clear out the old bits before
> we modify those bits as part of RMW
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    1 +
>  drivers/gpu/drm/i915/intel_display.c |   13 +++++++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8200e98..1a0f94e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
>  #define _CHV_PLL_DW9_CH0		0x8024
>  #define _CHV_PLL_DW9_CH1		0x81A4
>  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
>  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
>  #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 15904a8..a6b5786 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6176,11 +6176,24 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  		dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
>  		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
>  
> +		/* Program digital lock detect threshold */
> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
> +		dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
> +		dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);

Missing
 dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
here.

So I think to avoid such mistakes it's best to rewrite this too as:

val = read(PLL_DW9)
val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
val |= 0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT)
if (!bestm2_frac)
	val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
write(PLL_DW9, val);

> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
> +
>  	} else {
>  		/* M2 fraction division disable */
>  		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
>  		dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
>  		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> +
> +		/* Program digital lock detect threshold */
> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
> +		dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
> +		dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
> +		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
>  	}
>  
>  	/* Loop filter */
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV

[Ville Syrjälä]

On Tue, Mar 03, 2015 at 08:44:04PM +0530, Vijay Purushothaman wrote:
> This patch implements latest PHY changes in Gain, prop and int co-efficients
> based on the vco freq.
> 
> v2: Split the original changes into multiple smaller patches based on
> review by Ville
> 
> v3: Addressed Ville's review comments. Fixed the error introduced in v2.
> Clear the old bits before we modify those bits as part of RMW.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    2 ++
>  drivers/gpu/drm/i915/intel_display.c |   43 ++++++++++++++++++++++++----------
>  2 files changed, 33 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1a0f94e..5000184 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
>  
>  #define _CHV_PLL_DW8_CH0		0x8020
>  #define _CHV_PLL_DW8_CH1		0x81A0
> +#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
> +#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0xFF << 0)

This mask should be 10 bits AFAICS.

>  #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>  
>  #define _CHV_PLL_DW9_CH0		0x8024
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a6b5786..4e08a14 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6129,10 +6129,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	int pipe = crtc->pipe;
>  	int dpll_reg = DPLL(crtc->pipe);
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> -	u32 loopfilter, intcoeff;
> +	u32 loopfilter, tribuf_calcntr;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>  	u32 dpio_val;
> -	int refclk;
> +	int vco;
>  
>  	bestn = pipe_config->dpll.n;
>  	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
> @@ -6140,7 +6140,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	bestm2 = pipe_config->dpll.m2 >> 22;
>  	bestp1 = pipe_config->dpll.p1;
>  	bestp2 = pipe_config->dpll.p2;
> +	vco = pipe_config->dpll.vco;
>  	dpio_val = 0;
> +	loopfilter = 0;
>  
>  	/*
>  	 * Enable Refclk and SSC
> @@ -6197,18 +6199,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	}
>  
>  	/* Loop filter */
> -	refclk = i9xx_get_refclk(crtc, 0);
> -	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
> -		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
> -	if (refclk == 100000)
> -		intcoeff = 11;
> -	else if (refclk == 38400)
> -		intcoeff = 10;
> -	else
> -		intcoeff = 9;
> -	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
> +	if (vco == 5400000) {
> +		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 9;

Nit: inconsistent use of hex vs. decimal values for tribuf_calcntr.

> +	} else if (vco <= 6200000) {
> +		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0x9;
> +	} else if (vco <= 6480000) {
> +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0x8;
> +	} else {
> +		/* Not supported. Apply the same limits as in the max case */
> +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0;
> +	}
>  	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
>  
> +	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
> +	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
> +	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
> +
>  	/* AFC Recal */
>  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
>  			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/3] drm/i915: Disable M2 frac division for integer case

[Purushothaman, Vijay A]

On 3/3/2015 9:06 PM, Ville Syrjälä wrote:
> On Tue, Mar 03, 2015 at 08:41:54PM +0530, Vijay Purushothaman wrote:
>> v2 : Handle M2 frac division for both M2 frac and int cases
>>
>> v3 : Addressed Ville's review comments. Cleared the old bits for RMW
>>
>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h      |    1 +
>>   drivers/gpu/drm/i915/intel_display.c |   24 ++++++++++++++++++------
>>   2 files changed, 19 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 55143cb..8200e98 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
>>   #define  DPIO_CHV_FIRST_MOD		(0 << 8)
>>   #define  DPIO_CHV_SECOND_MOD		(1 << 8)
>>   #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
>> +#define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
>>   #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
>>   
>>   #define _CHV_PLL_DW6_CH0		0x8018
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 7298796..15904a8 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>>   	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>>   	u32 loopfilter, intcoeff;
>>   	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>> +	u32 dpio_val;
>>   	int refclk;
>>   
>>   	bestn = pipe_config->dpll.n;
>> @@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>>   	bestm2 = pipe_config->dpll.m2 >> 22;
>>   	bestp1 = pipe_config->dpll.p1;
>>   	bestp2 = pipe_config->dpll.p2;
>> +	dpio_val = 0;
>>   
>>   	/*
>>   	 * Enable Refclk and SSC
>> @@ -6163,13 +6165,23 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>>   			DPIO_CHV_M1_DIV_BY_2 |
>>   			1 << DPIO_CHV_N_DIV_SHIFT);
>>   
>> -	/* M2 fraction division */
>> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>> +	if (bestm2_frac) {
>> +		/* M2 fraction division */
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>>   
>> -	/* M2 fraction division enable */
>> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
>> -		       DPIO_CHV_FRAC_DIV_EN |
>> -		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
>> +		/* M2 fraction division enable */
>> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
>> +		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
>> +		dpio_val &= ~DPIO_CHV_FEEDFWD_GAIN_MASK;
>> +		dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
>> +
>> +	} else {
>> +		/* M2 fraction division disable */
>> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
>> +		dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
> You're not writing the feedfwd gain here. The register docs list it as
> 'Feedforwad gain for fractional mode/SSC mode PLL'. The SSC part there
> makes me think these bits might mean something even if the fractional
> divider is not used.
>
> At least I don't see any harm in setting it even if the fractional
> divider is not used. So with that in mind I'd probably write this as
> something like:
>
> val = read(PLL_DW3)
> val &= ~(FRAC_DIV_EN | FEEDFWD_GAIN_MASK)
> val |= 2 << FEEDFWD_GAIN_SHIFT;
> if (bestm2_trac)
> 	val |= FRAC_DIV_EN;
> write(PLL_DW3, val);
>
> This should also make it less likely we will accidentally update
> only one of the branches in the future when both need changing.
Makes sense. I will send v4 with this change and add your signed-off-by tag.

Thanks,
Vijay
>
>> +	}
>>   
>>   	/* Loop filter */
>>   	refclk = i9xx_get_refclk(crtc, 0);
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold

[Purushothaman, Vijay A]

On 3/3/2015 9:08 PM, Ville Syrjälä wrote:
> On Tue, Mar 03, 2015 at 08:43:12PM +0530, Vijay Purushothaman wrote:
>> Initialize lock detect threshold and select coarse threshold for the
>> case where M2 fraction division is disabled.
>>
>> v2: Split the changes into multiple smaller patches based on review by
>> Ville
>>
>> v3: Addressed rest of the review comments. Clear out the old bits before
>> we modify those bits as part of RMW
>>
>> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h      |    1 +
>>   drivers/gpu/drm/i915/intel_display.c |   13 +++++++++++++
>>   2 files changed, 14 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 8200e98..1a0f94e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
>>   #define _CHV_PLL_DW9_CH0		0x8024
>>   #define _CHV_PLL_DW9_CH1		0x81A4
>>   #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
>> +#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
>>   #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
>>   #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
>>   
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 15904a8..a6b5786 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6176,11 +6176,24 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>>   		dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
>>   		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
>>   
>> +		/* Program digital lock detect threshold */
>> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
>> +		dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
>> +		dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
> Missing
>   dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
> here.
>
> So I think to avoid such mistakes it's best to rewrite this too as:
>
> val = read(PLL_DW9)
> val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
> val |= 0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT)
> if (!bestm2_frac)
> 	val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
> write(PLL_DW9, val);

I will send v4 with this change and add your signed-off-by tag.

Thanks,
Vijay
>
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
>> +
>>   	} else {
>>   		/* M2 fraction division disable */
>>   		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
>>   		dpio_val &= ~DPIO_CHV_FRAC_DIV_EN;
>>   		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
>> +
>> +		/* Program digital lock detect threshold */
>> +		dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
>> +		dpio_val &= ~DPIO_CHV_INT_LOCK_THRESHOLD_MASK;
>> +		dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
>> +		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
>> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
>>   	}
>>   
>>   	/* Loop filter */
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/3] drm/i915: Disable M2 frac division for integer case

[Vijay Purushothaman]

v2 : Handle M2 frac division for both M2 frac and int cases

v3 : Addressed Ville's review comments. Cleared the old bits for RMW

v4 : Fix feedfwd gain (Ville)

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Signed-off-by: Ville Syrjala <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |   14 ++++++++++----
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 55143cb..8200e98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
 #define  DPIO_CHV_FIRST_MOD		(0 << 8)
 #define  DPIO_CHV_SECOND_MOD		(1 << 8)
 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
+#define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
 
 #define _CHV_PLL_DW6_CH0		0x8018
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7298796..c5a8725 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
 	u32 loopfilter, intcoeff;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+	u32 dpio_val;
 	int refclk;
 
 	bestn = pipe_config->dpll.n;
@@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	bestm2 = pipe_config->dpll.m2 >> 22;
 	bestp1 = pipe_config->dpll.p1;
 	bestp2 = pipe_config->dpll.p2;
+	dpio_val = 0;
 
 	/*
 	 * Enable Refclk and SSC
@@ -6164,12 +6166,16 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 			1 << DPIO_CHV_N_DIV_SHIFT);
 
 	/* M2 fraction division */
-	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+	if (bestm2_frac)
+		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
 
 	/* M2 fraction division enable */
-	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
-		       DPIO_CHV_FRAC_DIV_EN |
-		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
+	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+	if (bestm2_frac)
+		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
 
 	/* Loop filter */
 	refclk = i9xx_get_refclk(crtc, 0);
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/3] drm/i915: Initialize CHV digital lock detect threshold

[Vijay Purushothaman]

Initialize lock detect threshold and select coarse threshold for the
case where M2 fraction division is disabled.

v2: Split the changes into multiple smaller patches (Ville)
v3: Clear out the old bits before we modify those bits as RMW (Ville)
v4: Reset coarse threshold when M2 fraction is enabled (Ville)

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Signed-off-by: Ville Syrjala <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |    9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8200e98..1a0f94e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
 #define _CHV_PLL_DW9_CH0		0x8024
 #define _CHV_PLL_DW9_CH1		0x81A4
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c5a8725..6c5a5a9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6177,6 +6177,15 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
 
+	/* Program digital lock detect threshold */
+	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
+	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
+					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
+	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+	if (!bestm2_frac)
+		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
+
 	/* Loop filter */
 	refclk = i9xx_get_refclk(crtc, 0);
 	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV

[Vijay Purushothaman]

This patch implements latest PHY changes in Gain, prop and int co-efficients
based on the vco freq.

v2: Split the original changes into multiple smaller patches based on
review by Ville

v3: Addressed Ville's review comments. Fixed the error introduced in v2.
Clear the old bits before we modify those bits as part of RMW.

v4: TDC target cnt is 10 bits and not 8 bits (Ville)

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    2 ++
 drivers/gpu/drm/i915/intel_display.c |   43 ++++++++++++++++++++++++----------
 2 files changed, 33 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a0f94e..14b560b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
 
 #define _CHV_PLL_DW8_CH0		0x8020
 #define _CHV_PLL_DW8_CH1		0x81A0
+#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
+#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
 
 #define _CHV_PLL_DW9_CH0		0x8024
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6c5a5a9..3eb0946 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6129,10 +6129,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	int pipe = crtc->pipe;
 	int dpll_reg = DPLL(crtc->pipe);
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
-	u32 loopfilter, intcoeff;
+	u32 loopfilter, tribuf_calcntr;
 	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
 	u32 dpio_val;
-	int refclk;
+	int vco;
 
 	bestn = pipe_config->dpll.n;
 	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
@@ -6140,7 +6140,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	bestm2 = pipe_config->dpll.m2 >> 22;
 	bestp1 = pipe_config->dpll.p1;
 	bestp2 = pipe_config->dpll.p2;
+	vco = pipe_config->dpll.vco;
 	dpio_val = 0;
+	loopfilter = 0;
 
 	/*
 	 * Enable Refclk and SSC
@@ -6187,18 +6189,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
 
 	/* Loop filter */
-	refclk = i9xx_get_refclk(crtc, 0);
-	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
-		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
-	if (refclk == 100000)
-		intcoeff = 11;
-	else if (refclk == 38400)
-		intcoeff = 10;
-	else
-		intcoeff = 9;
-	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
+	if (vco == 5400000) {
+		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0x9;
+	} else if (vco <= 6200000) {
+		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0x9;
+	} else if (vco <= 6480000) {
+		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0x8;
+	} else {
+		/* Not supported. Apply the same limits as in the max case */
+		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
+		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
+		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		tribuf_calcntr = 0;
+	}
 	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
 
+	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
+	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
+	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
+
 	/* AFC Recal */
 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
 			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
-- 
1.7.9.5

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 3/3] drm/i915: Update prop, int co-eff and gain threshold for CHV

[Ville Syrjälä]

On Thu, Mar 05, 2015 at 07:33:08PM +0530, Vijay Purushothaman wrote:
> This patch implements latest PHY changes in Gain, prop and int co-efficients
> based on the vco freq.
> 
> v2: Split the original changes into multiple smaller patches based on
> review by Ville
> 
> v3: Addressed Ville's review comments. Fixed the error introduced in v2.
> Clear the old bits before we modify those bits as part of RMW.
> 
> v4: TDC target cnt is 10 bits and not 8 bits (Ville)
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    2 ++
>  drivers/gpu/drm/i915/intel_display.c |   43 ++++++++++++++++++++++++----------
>  2 files changed, 33 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1a0f94e..14b560b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1041,6 +1041,8 @@ enum skl_disp_power_wells {
>  
>  #define _CHV_PLL_DW8_CH0		0x8020
>  #define _CHV_PLL_DW8_CH1		0x81A0
> +#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
> +#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
>  #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>  
>  #define _CHV_PLL_DW9_CH0		0x8024
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6c5a5a9..3eb0946 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6129,10 +6129,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	int pipe = crtc->pipe;
>  	int dpll_reg = DPLL(crtc->pipe);
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> -	u32 loopfilter, intcoeff;
> +	u32 loopfilter, tribuf_calcntr;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
>  	u32 dpio_val;
> -	int refclk;
> +	int vco;
>  
>  	bestn = pipe_config->dpll.n;
>  	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
> @@ -6140,7 +6140,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	bestm2 = pipe_config->dpll.m2 >> 22;
>  	bestp1 = pipe_config->dpll.p1;
>  	bestp2 = pipe_config->dpll.p2;
> +	vco = pipe_config->dpll.vco;
>  	dpio_val = 0;
> +	loopfilter = 0;
>  
>  	/*
>  	 * Enable Refclk and SSC
> @@ -6187,18 +6189,35 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
>  
>  	/* Loop filter */
> -	refclk = i9xx_get_refclk(crtc, 0);
> -	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
> -		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
> -	if (refclk == 100000)
> -		intcoeff = 11;
> -	else if (refclk == 38400)
> -		intcoeff = 10;
> -	else
> -		intcoeff = 9;
> -	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
> +	if (vco == 5400000) {
> +		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0x9;
> +	} else if (vco <= 6200000) {
> +		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0x9;
> +	} else if (vco <= 6480000) {
> +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0x8;
> +	} else {
> +		/* Not supported. Apply the same limits as in the max case */
> +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> +		tribuf_calcntr = 0;
> +	}
>  	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
>  
> +	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
> +	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
> +	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
> +
>  	/* AFC Recal */
>  	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
>  			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz

[Daniel Vetter]

On Mon, Feb 16, 2015 at 01:21:34PM +0200, Ville Syrjälä wrote:
> On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
> > As per the recommendation from PHY team, limit the max vco supported in CHV to 6.48 GHz
> > 
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |    2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 3b0fe9f..4e710f6 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
> >  	 * them would make no difference.
> >  	 */
> >  	.dot = { .min = 25000 * 5, .max = 540000 * 5},
> > -	.vco = { .min = 4860000, .max = 6700000 },
> > +	.vco = { .min = 4860000, .max = 6480000 },
> 
> I have a patch here to reduce the minimum to 4.80 GHz, otherwise I can't
> get my 2560x1440 HDMI display working (241.5 MHz clock). With that change
> we still have a gap (233-240 MHz) in the frequencies we can produce.
> Reducing the max to 6.48 GHz will increase that gap to 216-240 MHz, which
> is a bit unfortunate. But if that's the recommendation we should follow
> it I suppose, and hope no HDMI displays will want such frequencies.
> 
> Is there an updated spreadsheet available with the new limits? Quite a
> few of the frequencies in the original spreadsheet did have vco>6.48
> GHz.
> 
> I any case this seems OK, so
> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

This one doesn't apply any more ... still needed?
-Daniel

> 
> >  	.n = { .min = 1, .max = 1 },
> >  	.m1 = { .min = 2, .max = 2 },
> >  	.m2 = { .min = 24 << 22, .max = 175 << 22 },
> > -- 
> > 1.7.9.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [v2 2/5] drm/i915: Limit max VCO supported in CHV to 6.48GHz

[Ville Syrjälä]

On Thu, Mar 05, 2015 at 04:52:56PM +0100, Daniel Vetter wrote:
> On Mon, Feb 16, 2015 at 01:21:34PM +0200, Ville Syrjälä wrote:
> > On Mon, Feb 16, 2015 at 03:07:59PM +0530, Vijay Purushothaman wrote:
> > > As per the recommendation from PHY team, limit the max vco supported in CHV to 6.48 GHz
> > > 
> > > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c |    2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 3b0fe9f..4e710f6 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
> > >  	 * them would make no difference.
> > >  	 */
> > >  	.dot = { .min = 25000 * 5, .max = 540000 * 5},
> > > -	.vco = { .min = 4860000, .max = 6700000 },
> > > +	.vco = { .min = 4860000, .max = 6480000 },
> > 
> > I have a patch here to reduce the minimum to 4.80 GHz, otherwise I can't
> > get my 2560x1440 HDMI display working (241.5 MHz clock). With that change
> > we still have a gap (233-240 MHz) in the frequencies we can produce.
> > Reducing the max to 6.48 GHz will increase that gap to 216-240 MHz, which
> > is a bit unfortunate. But if that's the recommendation we should follow
> > it I suppose, and hope no HDMI displays will want such frequencies.
> > 
> > Is there an updated spreadsheet available with the new limits? Quite a
> > few of the frequencies in the original spreadsheet did have vco>6.48
> > GHz.
> > 
> > I any case this seems OK, so
> > Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> This one doesn't apply any more ... still needed?

Supposedly, yes.

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/3] drm/i915: Disable M2 frac division for integer case

[Daniel Vetter]

On Thu, Mar 05, 2015 at 07:30:57PM +0530, Vijay Purushothaman wrote:
> v2 : Handle M2 frac division for both M2 frac and int cases
> 
> v3 : Addressed Ville's review comments. Cleared the old bits for RMW
> 
> v4 : Fix feedfwd gain (Ville)
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> Signed-off-by: Ville Syrjala <ville.syrjala@linux.intel.com>

sob != r-b. First is for having handled/forwarded/updated a patch, second
is review. And since I didn't see the r-b tag I thought these patches
still need more review, hence the delay in merging.

But all pulled into dinq now, thanks.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    1 +
>  drivers/gpu/drm/i915/intel_display.c |   14 ++++++++++----
>  2 files changed, 11 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 55143cb..8200e98 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
>  #define  DPIO_CHV_FIRST_MOD		(0 << 8)
>  #define  DPIO_CHV_SECOND_MOD		(1 << 8)
>  #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
> +#define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
>  #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
>  
>  #define _CHV_PLL_DW6_CH0		0x8018
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7298796..c5a8725 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6131,6 +6131,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>  	u32 loopfilter, intcoeff;
>  	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> +	u32 dpio_val;
>  	int refclk;
>  
>  	bestn = pipe_config->dpll.n;
> @@ -6139,6 +6140,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  	bestm2 = pipe_config->dpll.m2 >> 22;
>  	bestp1 = pipe_config->dpll.p1;
>  	bestp2 = pipe_config->dpll.p2;
> +	dpio_val = 0;
>  
>  	/*
>  	 * Enable Refclk and SSC
> @@ -6164,12 +6166,16 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
>  			1 << DPIO_CHV_N_DIV_SHIFT);
>  
>  	/* M2 fraction division */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> +	if (bestm2_frac)
> +		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
>  
>  	/* M2 fraction division enable */
> -	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
> -		       DPIO_CHV_FRAC_DIV_EN |
> -		       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
> +	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> +	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
> +	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
> +	if (bestm2_frac)
> +		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
> +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
>  
>  	/* Loop filter */
>  	refclk = i9xx_get_refclk(crtc, 0);
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx