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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 09/10] drm/i915/dvo: Extract intel_dvo_regs.h
Date: Tue, 22 Nov 2022 14:39:19 +0200	[thread overview]
Message-ID: <87bkozxix4.fsf@intel.com> (raw)
In-Reply-To: <20221122120825.26338-10-ville.syrjala@linux.intel.com>

On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the DVO port register definitons into their own header
> to declutter i915_reg.h a bit.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dvo.c      |  1 +
>  drivers/gpu/drm/i915/display/intel_dvo_regs.h | 54 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               | 44 ---------------
>  3 files changed, 55 insertions(+), 44 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_dvo_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index c590a92205f0..4a4b98bfce29 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -38,6 +38,7 @@
>  #include "intel_display_types.h"
>  #include "intel_dvo.h"
>  #include "intel_dvo_dev.h"
> +#include "intel_dvo_regs.h"
>  #include "intel_gmbus.h"
>  #include "intel_panel.h"
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo_regs.h b/drivers/gpu/drm/i915/display/intel_dvo_regs.h
> new file mode 100644
> index 000000000000..6f9058462850
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dvo_regs.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DVO_REGS_H__
> +#define __INTEL_DVO_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _DVOA			0x61120
> +#define _DVOB			0x61140
> +#define _DVOC			0x61160
> +#define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
> +#define   DVO_ENABLE				REG_BIT(31)
> +#define   DVO_PIPE_SEL_MASK			REG_BIT(30)
> +#define   DVO_PIPE_SEL(pipe)			REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
> +#define   DVO_PIPE_STALL_MASK			REG_GENMASK(29, 28)
> +#define   DVO_PIPE_STALL_UNUSED			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
> +#define   DVO_PIPE_STALL			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
> +#define   DVO_PIPE_STALL_TV			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
> +#define   DVO_INTERRUPT_SELECT			REG_BIT(27)
> +#define   DVO_DEDICATED_INT_ENABLE		REG_BIT(26)
> +#define   DVO_PRESERVE_MASK			REG_GENMASK(25, 24)
> +#define   DVO_USE_VGA_SYNC			REG_BIT(15)
> +#define   DVO_DATA_ORDER_MASK			REG_BIT(14)
> +#define   DVO_DATA_ORDER_I740			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
> +#define   DVO_DATA_ORDER_FP			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
> +#define   DVO_VSYNC_DISABLE			REG_BIT(11)
> +#define   DVO_HSYNC_DISABLE			REG_BIT(10)
> +#define   DVO_VSYNC_TRISTATE			REG_BIT(9)
> +#define   DVO_HSYNC_TRISTATE			REG_BIT(8)
> +#define   DVO_BORDER_ENABLE			REG_BIT(7)
> +#define   DVO_ACT_DATA_ORDER_MASK		REG_BIT(6)
> +#define   DVO_ACT_DATA_ORDER_RGGB		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
> +#define   DVO_ACT_DATA_ORDER_GBRG		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
> +#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
> +#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
> +#define   DVO_VSYNC_ACTIVE_HIGH			REG_BIT(4)
> +#define   DVO_HSYNC_ACTIVE_HIGH			REG_BIT(3)
> +#define   DVO_BLANK_ACTIVE_HIGH			REG_BIT(2)
> +#define   DVO_OUTPUT_CSTATE_PIXELS		REG_BIT(1) /* SDG only */
> +#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS		REG_BIT(0) /* SDG only */
> +
> +#define _DVOA_SRCDIM		0x61124
> +#define _DVOB_SRCDIM		0x61144
> +#define _DVOC_SRCDIM		0x61164
> +#define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
> +#define   DVO_SRCDIM_HORIZONTAL_MASK		REG_GENMASK(22, 12)
> +#define   DVO_SRCDIM_HORIZONTAL(x)		REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
> +#define   DVO_SRCDIM_VERTICAL_MASK		REG_GENMASK(10, 0)
> +#define   DVO_SRCDIM_VERTICAL(x)		REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
> +
> +#endif /* __INTEL_DVO_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 08fdc0107212..991e2a908314 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2575,50 +2575,6 @@
>  #define   SDVO_PIPE_SEL_MASK_CHV		(3 << 24)
>  #define   SDVO_PIPE_SEL_CHV(pipe)		((pipe) << 24)
>  
> -
> -/* DVO port control */
> -#define _DVOA			0x61120
> -#define _DVOB			0x61140
> -#define _DVOC			0x61160
> -#define DVO(port)		_MMIO_PORT((port), _DVOA, _DVOB)
> -#define   DVO_ENABLE				REG_BIT(31)
> -#define   DVO_PIPE_SEL_MASK			REG_BIT(30)
> -#define   DVO_PIPE_SEL(pipe)			REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
> -#define   DVO_PIPE_STALL_MASK			REG_GENMASK(29, 28)
> -#define   DVO_PIPE_STALL_UNUSED			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
> -#define   DVO_PIPE_STALL			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
> -#define   DVO_PIPE_STALL_TV			REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
> -#define   DVO_INTERRUPT_SELECT			REG_BIT(27)
> -#define   DVO_DEDICATED_INT_ENABLE		REG_BIT(26)
> -#define   DVO_PRESERVE_MASK			REG_GENMASK(25, 24)
> -#define   DVO_USE_VGA_SYNC			REG_BIT(15)
> -#define   DVO_DATA_ORDER_MASK			REG_BIT(14)
> -#define   DVO_DATA_ORDER_I740			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
> -#define   DVO_DATA_ORDER_FP			REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
> -#define   DVO_VSYNC_DISABLE			REG_BIT(11)
> -#define   DVO_HSYNC_DISABLE			REG_BIT(10)
> -#define   DVO_VSYNC_TRISTATE			REG_BIT(9)
> -#define   DVO_HSYNC_TRISTATE			REG_BIT(8)
> -#define   DVO_BORDER_ENABLE			REG_BIT(7)
> -#define   DVO_ACT_DATA_ORDER_MASK		REG_BIT(6)
> -#define   DVO_ACT_DATA_ORDER_RGGB		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
> -#define   DVO_ACT_DATA_ORDER_GBRG		REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
> -#define   DVO_ACT_DATA_ORDER_GBRG_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
> -#define   DVO_ACT_DATA_ORDER_RGGB_ERRATA	REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
> -#define   DVO_VSYNC_ACTIVE_HIGH			REG_BIT(4)
> -#define   DVO_HSYNC_ACTIVE_HIGH			REG_BIT(3)
> -#define   DVO_BLANK_ACTIVE_HIGH			REG_BIT(2)
> -#define   DVO_OUTPUT_CSTATE_PIXELS		REG_BIT(1) /* SDG only */
> -#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS		REG_BIT(0) /* SDG only */
> -#define _DVOA_SRCDIM		0x61124
> -#define _DVOB_SRCDIM		0x61144
> -#define _DVOC_SRCDIM		0x61164
> -#define DVO_SRCDIM(port)	_MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
> -#define   DVO_SRCDIM_HORIZONTAL_MASK		REG_GENMASK(22, 12)
> -#define   DVO_SRCDIM_HORIZONTAL(x)		REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x))
> -#define   DVO_SRCDIM_VERTICAL_MASK		REG_GENMASK(10, 0)
> -#define   DVO_SRCDIM_VERTICAL(x)		REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x))
> -
>  /* LVDS port control */
>  #define LVDS			_MMIO(0x61180)
>  /*

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-11-22 12:39 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-22 12:08 [Intel-gfx] [PATCH 00/10] drm/i915/dvo: Further DVO fixes/cleanups Ville Syrjala
2022-11-22 12:08 ` [Intel-gfx] [PATCH 01/10] drm/i915/dvo/ch7xxx: Fix suspend/resume Ville Syrjala
2022-11-22 12:31   ` Jani Nikula
2022-11-23 14:52     ` Ville Syrjälä
2022-11-22 12:08 ` [Intel-gfx] [PATCH 02/10] drm/i915/dvo/sil164: Nuke pointless return statements Ville Syrjala
2022-11-22 12:32   ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 03/10] drm/i915/dvo/sil164: Fix suspend/resume Ville Syrjala
2022-11-22 12:32   ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 04/10] drm/i915/dvo: Parametrize DVO/DVO_SRCDIM registers Ville Syrjala
2022-11-22 12:33   ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 05/10] drm/i915/dvo: Define a few more DVO register bits Ville Syrjala
2022-11-22 12:33   ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 06/10] drm/i915/dvo: Rename the "active data order" bits Ville Syrjala
2022-11-22 12:33   ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 07/10] drm/i915/dvo: Use REG_BIT() & co. for DVO registers Ville Syrjala
2022-11-22 12:35   ` Jani Nikula
2022-11-22 12:36     ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 08/10] drm/i915/dvo: Use intel_de_rmw() for DVO enable/disable Ville Syrjala
2022-11-22 12:38   ` Jani Nikula
2022-11-22 12:08 ` [Intel-gfx] [PATCH 09/10] drm/i915/dvo: Extract intel_dvo_regs.h Ville Syrjala
2022-11-22 12:39   ` Jani Nikula [this message]
2022-11-22 12:08 ` [Intel-gfx] [PATCH 10/10] drm/i915/dvo: Log about what was detected on which DVO port Ville Syrjala
2022-11-22 12:39   ` Jani Nikula
2022-11-22 15:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dvo: Further DVO fixes/cleanups Patchwork
2022-11-22 15:55 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-11-22 16:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-11-23  0:49 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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