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Wed, 09 Dec 2020 10:32:05 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id r82sm4851253wma.18.2020.12.09.10.32.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Dec 2020 10:32:03 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 26D831FF7E; Wed, 9 Dec 2020 18:32:03 +0000 (GMT) References: <20201208194839.31305-1-cfontana@suse.de> <20201208194839.31305-28-cfontana@suse.de> <87sg8fcf3z.fsf@linaro.org> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Claudio Fontana Subject: Re: [RFC v9 27/32] accel: replace struct CpusAccel with AccelOpsClass Date: Wed, 09 Dec 2020 18:30:30 +0000 In-reply-to: Message-ID: <87blf2de58.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Durrant , Jason Wang , qemu-devel@nongnu.org, Peter Xu , haxm-team@intel.com, Colin Xu , Olaf Hering , Stefano Stabellini , Bruce Rogers , "Emilio G . Cota" , Anthony Perard , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Laurent Vivier , Thomas Huth , Eduardo Habkost , Richard Henderson , Cameron Esfahani , Dario Faggioli , Roman Bolshakov , Sunil Muthuswamy , Marcelo Tosatti , Wenchao Wang , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Claudio Fontana writes: > On 12/9/20 1:54 PM, Alex Benn=C3=A9e wrote: >>=20 >> Claudio Fontana writes: >>=20 >>> centralize the registration of the cpus.c module >>> accelerator operations in accel/accel-softmmu.c >>> >>> Signed-off-by: Claudio Fontana >> >>> diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c >>> index e335f9f155..38a58ab271 100644 >>> --- a/accel/tcg/tcg-cpus.c >>> +++ b/accel/tcg/tcg-cpus.c >>> @@ -35,6 +35,9 @@ >>> #include "hw/boards.h" >>>=20=20 >>> #include "tcg-cpus.h" >>> +#include "tcg-cpus-mttcg.h" >>> +#include "tcg-cpus-rr.h" >>> +#include "tcg-cpus-icount.h" >>>=20=20 >>> /* common functionality among all TCG variants */ >>>=20=20 >>> @@ -80,3 +83,43 @@ void tcg_cpus_handle_interrupt(CPUState *cpu, int ma= sk) >>> qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); >>> } >>> } >>> + >>> +static void tcg_cpus_ops_init(AccelOpsClass *ops) >>> +{ >>> + if (qemu_tcg_mttcg_enabled()) { >>> + ops->create_vcpu_thread =3D mttcg_start_vcpu_thread; >>> + ops->kick_vcpu_thread =3D mttcg_kick_vcpu_thread; >>> + ops->handle_interrupt =3D tcg_cpus_handle_interrupt; >>> + >>> + } else if (icount_enabled()) { >>> + ops->create_vcpu_thread =3D rr_start_vcpu_thread; >>> + ops->kick_vcpu_thread =3D rr_kick_vcpu_thread; >>> + ops->handle_interrupt =3D icount_handle_interrupt; >>> + ops->get_virtual_clock =3D icount_get; >>> + ops->get_elapsed_ticks =3D icount_get; >>> + >>> + } else { >>> + ops->create_vcpu_thread =3D rr_start_vcpu_thread; >>> + ops->kick_vcpu_thread =3D rr_kick_vcpu_thread; >>> + ops->handle_interrupt =3D tcg_cpus_handle_interrupt; >>> + } >>> +} >>=20 >> Aren't we going backwards here by having a global function aware of the >> different accelerator types rather than encapsulating this is the >> particular accelerator machinery? >>=20 >> >>=20 > > Now I got your point. > > The ideal would be to have three classes. One called tcg-mttcg, one tcg-i= count, one tcg-rr. > The problem: backward compatibility I think, since currently we have only= one accel, "tcg". > > But, hmm maybe fixable, I'll take a look. Yeah I was wondering if we were going to have subclasses for each "type" of TCG. But now I'm wondering if that even makes sense. Will we ever want to built a TCG enabled binary that say doesn't do icount? Maybe not - having a single AccelOpsClass which runs in 3 modes will probably do for now. > > Thanks! > > Claudio --=20 Alex Benn=C3=A9e