From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59002) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bjKWr-00020I-5v for qemu-devel@nongnu.org; Mon, 12 Sep 2016 02:15:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bjKWn-00051C-Of for qemu-devel@nongnu.org; Mon, 12 Sep 2016 02:15:40 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:43790 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bjKWn-00050j-Eb for qemu-devel@nongnu.org; Mon, 12 Sep 2016 02:15:37 -0400 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u8C6D9xC062581 for ; Mon, 12 Sep 2016 02:15:37 -0400 Received: from e28smtp02.in.ibm.com (e28smtp02.in.ibm.com [125.16.236.2]) by mx0a-001b2d01.pphosted.com with ESMTP id 25ce5wq425-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 12 Sep 2016 02:15:36 -0400 Received: from localhost by e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 12 Sep 2016 11:45:33 +0530 From: Nikunj A Dadhania In-Reply-To: <1473660530.8689.240.camel@kernel.crashing.org> References: <1473659314-11813-1-git-send-email-nikunj@linux.vnet.ibm.com> <1473659314-11813-4-git-send-email-nikunj@linux.vnet.ibm.com> <1473660530.8689.240.camel@kernel.crashing.org> Date: Mon, 12 Sep 2016 11:45:22 +0530 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Message-Id: <87bmztskxx.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> Subject: Re: [Qemu-devel] [PATCH v3 3/3] target-ppc: tlbie should have global effect List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt , qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Cc: alex.bennee@linaro.org, qemu-devel@nongnu.org, rth@twiddle.net Benjamin Herrenschmidt writes: > On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote: >> diff --git a/target-ppc/translate.c b/target-ppc/translate.c >> index 5026804..d96ff66 100644 >> --- a/target-ppc/translate.c >> +++ b/target-ppc/translate.c >> @@ -4448,6 +4448,7 @@ static void gen_tlbie(DisasContext *ctx) >> =C2=A0#if defined(CONFIG_USER_ONLY) >> =C2=A0=C2=A0=C2=A0=C2=A0 GEN_PRIV; >> =C2=A0#else >> +=C2=A0=C2=A0=C2=A0 TCGv_i32 t1; >> =C2=A0=C2=A0=C2=A0=C2=A0 CHK_HV; >> =C2=A0 >> =C2=A0=C2=A0=C2=A0=C2=A0 if (NARROW_MODE(ctx)) { >> @@ -4458,6 +4459,11 @@ static void gen_tlbie(DisasContext *ctx) >> =C2=A0=C2=A0=C2=A0=C2=A0 } else { >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 gen_helper_tlbie(cpu_en= v, cpu_gpr[rB(ctx->opcode)]); >> =C2=A0=C2=A0=C2=A0=C2=A0 } >> +=C2=A0=C2=A0=C2=A0 t1 =3D tcg_temp_new_i32(); >> +=C2=A0=C2=A0=C2=A0 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tl= b_need_flush)); >> +=C2=A0=C2=A0=C2=A0 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); >> +=C2=A0=C2=A0=C2=A0 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tl= b_need_flush)); >> +=C2=A0=C2=A0=C2=A0 tcg_temp_free_i32(t1); >> =C2=A0#endif /* defined(CONFIG_USER_ONLY) */ > > Why not do this in the helper ?=C2=A0 No particular reason though, I can do it there as well. Regards Nikunj