From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46560) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjnG6-0002oT-Sm for qemu-devel@nongnu.org; Wed, 07 Oct 2015 07:51:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZjnG3-0001eE-JW for qemu-devel@nongnu.org; Wed, 07 Oct 2015 07:51:46 -0400 Received: from mail-wi0-f178.google.com ([209.85.212.178]:33942) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjnG3-0001ds-CM for qemu-devel@nongnu.org; Wed, 07 Oct 2015 07:51:43 -0400 Received: by wicfx3 with SMTP id fx3so208450570wic.1 for ; Wed, 07 Oct 2015 04:51:42 -0700 (PDT) References: <1443911939-2825-1-git-send-email-edgar.iglesias@gmail.com> <1443911939-2825-2-git-send-email-edgar.iglesias@gmail.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1443911939-2825-2-git-send-email-edgar.iglesias@gmail.com> Date: Wed, 07 Oct 2015 12:51:40 +0100 Message-ID: <87bncayjzn.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v3 1/9] target-arm: Add HPFAR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, qemu-devel@nongnu.org, agraf@suse.de, laurent.desnogues@gmail.com, serge.fdrv@gmail.com Edgar E. Iglesias writes: > From: "Edgar E. Iglesias" > > Signed-off-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 1 + > target-arm/helper.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index cc1578c..895f2c2 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -278,6 +278,7 @@ typedef struct CPUARMState { > }; > uint64_t far_el[4]; > }; > + uint64_t hpfar_el2; > union { /* Translation result. */ > struct { > uint64_t _unused_par_0; > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 8367997..5a5e5f0 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, > .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, > + .type = ARM_CP_CONST, .resetvalue = 0 }, So what happens if access_el3_aa32ns_aa64any thinks it is OK to access the register from EL3 when there is no EL2? What ensures we get RES0? > REGINFO_SENTINEL > }; > > @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .resetvalue = 0, > .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, > #endif > + { .name = "HPFAR", .state = ARM_CP_STATE_AA32, > + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, .accessfn = access_el3_aa32ns, > + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, > + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, > REGINFO_SENTINEL > }; Otherwise: Reviewed-by: Alex Bennée -- Alex Bennée