From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9B77C433EF for ; Sun, 21 Nov 2021 19:11:37 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 242E54083E; Sun, 21 Nov 2021 14:11:37 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OE-Of20KIuAK; Sun, 21 Nov 2021 14:11:35 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id C222F4A7FD; Sun, 21 Nov 2021 14:11:35 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id A33DD4083E for ; Sun, 21 Nov 2021 14:11:34 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jFFI6H6acYSI for ; Sun, 21 Nov 2021 14:11:33 -0500 (EST) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id CEB3C4079A for ; Sun, 21 Nov 2021 14:11:32 -0500 (EST) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C688560698; Sun, 21 Nov 2021 19:11:31 +0000 (UTC) Received: from 82-132-235-208.dab.02.net ([82.132.235.208] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mosFN-006vRk-HW; Sun, 21 Nov 2021 19:11:29 +0000 Date: Sun, 21 Nov 2021 19:11:30 +0000 Message-ID: <87czmts4rh.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Subject: Re: [PATCH 3/4] KVM: arm64: Add KVM_ARM_VCPU_PMU_V3_SET_PMU attribute In-Reply-To: <20211115165041.194884-4-alexandru.elisei@arm.com> References: <20211115165041.194884-1-alexandru.elisei@arm.com> <20211115165041.194884-4-alexandru.elisei@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 82.132.235.208 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, peter.maydell@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Mon, 15 Nov 2021 16:50:40 +0000, Alexandru Elisei wrote: > > When KVM creates an event and there are more than one PMUs present on the > system, perf_init_event() will go through the list of available PMUs and > will choose the first one that can create the event. The order of the PMUs > in the PMU list depends on the probe order, which can change under various > circumstances, for example if the order of the PMU nodes change in the DTB > or if asynchronous driver probing is enabled on the kernel command line > (with the driver_async_probe=armv8-pmu option). > > Another consequence of this approach is that, on heteregeneous systems, > all virtual machines that KVM creates will use the same PMU. This might > cause unexpected behaviour for userspace: when a VCPU is executing on > the physical CPU that uses this PMU, PMU events in the guest work > correctly; but when the same VCPU executes on another CPU, PMU events in > the guest will suddenly stop counting. > > Fortunately, perf core allows user to specify on which PMU to create an > event by using the perf_event_attr->type field, which is used by > perf_init_event() as an index in the radix tree of available PMUs. > > Add the KVM_ARM_VCPU_PMU_V3_CTRL(KVM_ARM_VCPU_PMU_V3_SET_PMU) VCPU > attribute to allow userspace to specify the arm_pmu that KVM will use when > creating events for that VCPU. KVM will make no attempt to run the VCPU on > the physical CPUs that share this PMU, leaving it up to userspace to > manage the VCPU threads' affinity accordingly. > > Signed-off-by: Alexandru Elisei > --- > Documentation/virt/kvm/devices/vcpu.rst | 25 ++++++++++++++++++++ > arch/arm64/include/uapi/asm/kvm.h | 1 + > arch/arm64/kvm/pmu-emul.c | 31 +++++++++++++++++++++++-- > include/kvm/arm_pmu.h | 1 + > tools/arch/arm64/include/uapi/asm/kvm.h | 1 + > 5 files changed, 57 insertions(+), 2 deletions(-) > > diff --git a/Documentation/virt/kvm/devices/vcpu.rst b/Documentation/virt/kvm/devices/vcpu.rst > index 60a29972d3f1..59ac382af59a 100644 > --- a/Documentation/virt/kvm/devices/vcpu.rst > +++ b/Documentation/virt/kvm/devices/vcpu.rst > @@ -104,6 +104,31 @@ hardware event. Filtering event 0x1E (CHAIN) has no effect either, as it > isn't strictly speaking an event. Filtering the cycle counter is possible > using event 0x11 (CPU_CYCLES). > > +1.4 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_SET_PMU > +------------------------------------------ > + > +:Parameters: in kvm_device_attr.addr the address to an int representing the PMU > + identifier. > + > +:Returns: > + > + ======= =============================================== > + -EBUSY PMUv3 already initialized > + -EFAULT Error accessing the PMU identifier > + -EINVAL PMU not found or PMU name longer than PAGE_SIZE > + -ENODEV PMUv3 not supported or GIC not initialized > + -ENOMEM Could not allocate memory > + ======= =============================================== > + > +Request that the VCPU uses the specified hardware PMU when creating guest events > +for the purpose of PMU emulation. The PMU identifier can be read from the "type" > +file for the desired PMU instance under /sys/devices (or, equivalent, > +/sys/bus/even_source). This attribute is particularly useful on heterogeneous > +systems where there are at least two PMUs on the system. nit: CPU PMUs. A number of systems have 'uncore' PMUs which KVM totally ignores. > + > +Note that KVM will not make any attempts to run the VCPU on the physical CPUs > +associated with the PMU specified by this attribute. This is entirely left to > +userspace. > > 2. GROUP: KVM_ARM_VCPU_TIMER_CTRL > ================================= > diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h > index b3edde68bc3e..1d0a0a2a9711 100644 > --- a/arch/arm64/include/uapi/asm/kvm.h > +++ b/arch/arm64/include/uapi/asm/kvm.h > @@ -362,6 +362,7 @@ struct kvm_arm_copy_mte_tags { > #define KVM_ARM_VCPU_PMU_V3_IRQ 0 > #define KVM_ARM_VCPU_PMU_V3_INIT 1 > #define KVM_ARM_VCPU_PMU_V3_FILTER 2 > +#define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 > #define KVM_ARM_VCPU_TIMER_CTRL 1 > #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 > #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index dab335d17409..53cedeb5dbf6 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -602,6 +602,7 @@ static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx) > static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) > { > struct kvm_pmu *pmu = &vcpu->arch.pmu; > + struct arm_pmu *arm_pmu = pmu->arm_pmu; > struct kvm_pmc *pmc; > struct perf_event *event; > struct perf_event_attr attr; > @@ -637,8 +638,7 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) > return; > > memset(&attr, 0, sizeof(struct perf_event_attr)); > - attr.type = PERF_TYPE_RAW; > - attr.size = sizeof(attr); > + attr.type = arm_pmu ? arm_pmu->pmu.type : PERF_TYPE_RAW; > attr.pinned = 1; > attr.disabled = !kvm_pmu_counter_is_enabled(vcpu, pmc->idx); > attr.exclude_user = data & ARMV8_PMU_EXCLUDE_EL0 ? 1 : 0; > @@ -941,6 +941,23 @@ static bool pmu_irq_is_valid(struct kvm *kvm, int irq) > return true; > } > > +static int kvm_arm_pmu_v3_set_pmu(struct kvm_vcpu *vcpu, int pmu_id) > +{ > + struct kvm_pmu *kvm_pmu = &vcpu->arch.pmu; > + struct arm_pmu_entry *entry; > + struct arm_pmu *arm_pmu; > + > + list_for_each_entry(entry, &arm_pmus, entry) { > + arm_pmu = entry->arm_pmu; > + if (arm_pmu->pmu.type == pmu_id) { > + kvm_pmu->arm_pmu = arm_pmu; > + return 0; > + } > + } How does this work when a new CPU gets hotplugged on, bringing a new PMU type along? It doesn't seem safe to parse this list without any locking. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A317C433EF for ; Sun, 21 Nov 2021 19:13:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4gnSOn7S4IwhKFju/QWn/xIOtpNH4Bi/6DjTfrYWa/0=; b=TLxyE8kvl+GcgM PZHtjZ99+v8FcTcAWCYcVCdYM/+i4VO4PtTkFSa5ptHJVcCsXgKORGz8u/HGt6QGkx9HZiF3jO1va x7IfliCFBmA85iHjG4r2goJQFYc9bCN0eMFhrOIFhKDyyc+k25QOpRrF5avcvg8s3M10gnBBcPsX/ lqOiT7ktaRnQiENUeKFfcWY3y+RCTzRn/3VYqCsacEpxPubUIOCptcJDyxYCBI7Wtjx/nvT2cbvoU 5ptsFctrhJTieJnyGXnSZbc3k/WU6OD4txpar+H4YNDfyUI+sqebu6GBe457rU8/4GViPpxhINiYv Z3rdP15lcsNynlHR2phw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mosFU-00EDi7-3W; Sun, 21 Nov 2021 19:11:36 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mosFQ-00EDhg-1c for linux-arm-kernel@lists.infradead.org; Sun, 21 Nov 2021 19:11:33 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C688560698; Sun, 21 Nov 2021 19:11:31 +0000 (UTC) Received: from 82-132-235-208.dab.02.net ([82.132.235.208] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mosFN-006vRk-HW; Sun, 21 Nov 2021 19:11:29 +0000 Date: Sun, 21 Nov 2021 19:11:30 +0000 Message-ID: <87czmts4rh.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Cc: james.morse@arm.com, suzuki.poulose@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, peter.maydell@linaro.org Subject: Re: [PATCH 3/4] KVM: arm64: Add KVM_ARM_VCPU_PMU_V3_SET_PMU attribute In-Reply-To: <20211115165041.194884-4-alexandru.elisei@arm.com> References: <20211115165041.194884-1-alexandru.elisei@arm.com> <20211115165041.194884-4-alexandru.elisei@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 82.132.235.208 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, james.morse@arm.com, suzuki.poulose@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, peter.maydell@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211121_111132_175579_9C854F29 X-CRM114-Status: GOOD ( 42.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 15 Nov 2021 16:50:40 +0000, Alexandru Elisei wrote: > > When KVM creates an event and there are more than one PMUs present on the > system, perf_init_event() will go through the list of available PMUs and > will choose the first one that can create the event. The order of the PMUs > in the PMU list depends on the probe order, which can change under various > circumstances, for example if the order of the PMU nodes change in the DTB > or if asynchronous driver probing is enabled on the kernel command line > (with the driver_async_probe=armv8-pmu option). > > Another consequence of this approach is that, on heteregeneous systems, > all virtual machines that KVM creates will use the same PMU. This might > cause unexpected behaviour for userspace: when a VCPU is executing on > the physical CPU that uses this PMU, PMU events in the guest work > correctly; but when the same VCPU executes on another CPU, PMU events in > the guest will suddenly stop counting. > > Fortunately, perf core allows user to specify on which PMU to create an > event by using the perf_event_attr->type field, which is used by > perf_init_event() as an index in the radix tree of available PMUs. > > Add the KVM_ARM_VCPU_PMU_V3_CTRL(KVM_ARM_VCPU_PMU_V3_SET_PMU) VCPU > attribute to allow userspace to specify the arm_pmu that KVM will use when > creating events for that VCPU. KVM will make no attempt to run the VCPU on > the physical CPUs that share this PMU, leaving it up to userspace to > manage the VCPU threads' affinity accordingly. > > Signed-off-by: Alexandru Elisei > --- > Documentation/virt/kvm/devices/vcpu.rst | 25 ++++++++++++++++++++ > arch/arm64/include/uapi/asm/kvm.h | 1 + > arch/arm64/kvm/pmu-emul.c | 31 +++++++++++++++++++++++-- > include/kvm/arm_pmu.h | 1 + > tools/arch/arm64/include/uapi/asm/kvm.h | 1 + > 5 files changed, 57 insertions(+), 2 deletions(-) > > diff --git a/Documentation/virt/kvm/devices/vcpu.rst b/Documentation/virt/kvm/devices/vcpu.rst > index 60a29972d3f1..59ac382af59a 100644 > --- a/Documentation/virt/kvm/devices/vcpu.rst > +++ b/Documentation/virt/kvm/devices/vcpu.rst > @@ -104,6 +104,31 @@ hardware event. Filtering event 0x1E (CHAIN) has no effect either, as it > isn't strictly speaking an event. Filtering the cycle counter is possible > using event 0x11 (CPU_CYCLES). > > +1.4 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_SET_PMU > +------------------------------------------ > + > +:Parameters: in kvm_device_attr.addr the address to an int representing the PMU > + identifier. > + > +:Returns: > + > + ======= =============================================== > + -EBUSY PMUv3 already initialized > + -EFAULT Error accessing the PMU identifier > + -EINVAL PMU not found or PMU name longer than PAGE_SIZE > + -ENODEV PMUv3 not supported or GIC not initialized > + -ENOMEM Could not allocate memory > + ======= =============================================== > + > +Request that the VCPU uses the specified hardware PMU when creating guest events > +for the purpose of PMU emulation. The PMU identifier can be read from the "type" > +file for the desired PMU instance under /sys/devices (or, equivalent, > +/sys/bus/even_source). This attribute is particularly useful on heterogeneous > +systems where there are at least two PMUs on the system. nit: CPU PMUs. A number of systems have 'uncore' PMUs which KVM totally ignores. > + > +Note that KVM will not make any attempts to run the VCPU on the physical CPUs > +associated with the PMU specified by this attribute. This is entirely left to > +userspace. > > 2. GROUP: KVM_ARM_VCPU_TIMER_CTRL > ================================= > diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h > index b3edde68bc3e..1d0a0a2a9711 100644 > --- a/arch/arm64/include/uapi/asm/kvm.h > +++ b/arch/arm64/include/uapi/asm/kvm.h > @@ -362,6 +362,7 @@ struct kvm_arm_copy_mte_tags { > #define KVM_ARM_VCPU_PMU_V3_IRQ 0 > #define KVM_ARM_VCPU_PMU_V3_INIT 1 > #define KVM_ARM_VCPU_PMU_V3_FILTER 2 > +#define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 > #define KVM_ARM_VCPU_TIMER_CTRL 1 > #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 > #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index dab335d17409..53cedeb5dbf6 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -602,6 +602,7 @@ static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx) > static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) > { > struct kvm_pmu *pmu = &vcpu->arch.pmu; > + struct arm_pmu *arm_pmu = pmu->arm_pmu; > struct kvm_pmc *pmc; > struct perf_event *event; > struct perf_event_attr attr; > @@ -637,8 +638,7 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) > return; > > memset(&attr, 0, sizeof(struct perf_event_attr)); > - attr.type = PERF_TYPE_RAW; > - attr.size = sizeof(attr); > + attr.type = arm_pmu ? arm_pmu->pmu.type : PERF_TYPE_RAW; > attr.pinned = 1; > attr.disabled = !kvm_pmu_counter_is_enabled(vcpu, pmc->idx); > attr.exclude_user = data & ARMV8_PMU_EXCLUDE_EL0 ? 1 : 0; > @@ -941,6 +941,23 @@ static bool pmu_irq_is_valid(struct kvm *kvm, int irq) > return true; > } > > +static int kvm_arm_pmu_v3_set_pmu(struct kvm_vcpu *vcpu, int pmu_id) > +{ > + struct kvm_pmu *kvm_pmu = &vcpu->arch.pmu; > + struct arm_pmu_entry *entry; > + struct arm_pmu *arm_pmu; > + > + list_for_each_entry(entry, &arm_pmus, entry) { > + arm_pmu = entry->arm_pmu; > + if (arm_pmu->pmu.type == pmu_id) { > + kvm_pmu->arm_pmu = arm_pmu; > + return 0; > + } > + } How does this work when a new CPU gets hotplugged on, bringing a new PMU type along? It doesn't seem safe to parse this list without any locking. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel