From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72A5CC04FF3 for ; Mon, 24 May 2021 17:18:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4922C6109F for ; Mon, 24 May 2021 17:18:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233302AbhEXRTa (ORCPT ); Mon, 24 May 2021 13:19:30 -0400 Received: from mail.kernel.org ([198.145.29.99]:52572 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232543AbhEXRTa (ORCPT ); Mon, 24 May 2021 13:19:30 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 54AD5610A6; Mon, 24 May 2021 17:18:02 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1llEDI-003Ifj-8k; Mon, 24 May 2021 18:18:00 +0100 Date: Mon, 24 May 2021 18:17:59 +0100 Message-ID: <87cztgvyns.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, James Morse , Suzuki K Poulose , Eric Auger , Hector Martin , Mark Rutland , kernel-team@android.com Subject: Re: [PATCH v3 4/9] KVM: arm64: vgic: Let an interrupt controller advertise lack of HW deactivation In-Reply-To: <417846b3-ff5e-1832-82b2-3e0064275944@arm.com> References: <20210510134824.1910399-1-maz@kernel.org> <20210510134824.1910399-5-maz@kernel.org> <417846b3-ff5e-1832-82b2-3e0064275944@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, james.morse@arm.com, suzuki.poulose@arm.com, eric.auger@redhat.com, marcan@marcan.st, mark.rutland@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Alex, On Fri, 21 May 2021 18:01:05 +0100, Alexandru Elisei wrote: > > Hi Marc, > > On 5/10/21 2:48 PM, Marc Zyngier wrote: > > The vGIC, as architected by ARM, allows a virtual interrupt to > > trigger the deactivation of a physical interrupt. This allows > > the following interrupt to be delivered without requiring an exit. > > If I got this right, the AIC doesn't implement/ignores the s/AIC/M1 CPU/ > ICH_LR_EL2.HW bit. Does it mean that the CPU IF behaves as if HW = > 0b0, meaning it asserts a maintenance interrupt on virtual interrupt > deactivation when ICH_LR_EL2.EOI = 0b1? I assume that's the case, > just double checking. Yes, that's what it looks like. > I am wondering what would happen if we come across an interrupt > controller where the CPU IF cannot assert a maintenance interrupt at > all and we rely on the EOI bit to take us out of the guest to > deactivate the HW interrupt. That'd be broken, and we wouldn't be able to support such an implementation, at least not in configuration such as CPU isolation. > I have to say that it looks a bit strange to start relying on the > maintenance interrupt to emulate interrupt deactivate for hardware > interrupts, but at the same timer allowing an interrupt controller > without a maintenance interrupt. We are not allowing a vGIC without a maintenance interrupt. We are actively mandating it. The M1 does have a working per-CPU maintenance interrupt. It just isn't wired into an interrupt controller, which means we can't mask it. But it is otherwise perfectly functional. > Other than that, this idea sounds like the best thing to do > considering the circumstances, I certainly can't think of anything > better. > > > > > However, some implementations have choosen not to implement this, > > meaning that we will need some unsavoury workarounds to deal with this. > > > > On detecting such a case, taint the kernel and spit a nastygram. > > We'll deal with this in later patches. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/vgic/vgic-init.c | 10 ++++++++++ > > include/kvm/arm_vgic.h | 3 +++ > > include/linux/irqchip/arm-vgic-info.h | 2 ++ > > 3 files changed, 15 insertions(+) > > > > diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c > > index 9fd23f32aa54..5b06a9970a57 100644 > > --- a/arch/arm64/kvm/vgic/vgic-init.c > > +++ b/arch/arm64/kvm/vgic/vgic-init.c > > @@ -524,6 +524,16 @@ int kvm_vgic_hyp_init(void) > > if (!gic_kvm_info) > > return -ENODEV; > > > > + /* > > + * If we get one of these oddball non-GICs, taint the kernel, > > + * as we have no idea of how they *really* behave. > > + */ > > + if (gic_kvm_info->no_hw_deactivation) { > > + kvm_info("Non-architectural vgic, tainting kernel\n"); > > + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); > > + kvm_vgic_global_state.no_hw_deactivation = true; > > + } > > IMO, since this means we're going to rely even more on the > maintenance interrupt (not just for software emulation of level > sensitive interrupts), I think there should be some sort of > dependency on having something that resembles a working maintenance > interrupt. But the timer interrupt is exactly a SW emulation of a level sensitive interrupt in this context. And the maintenance interrupt is still required to use the vGIC. Thanks, M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58313C04FF3 for ; Mon, 24 May 2021 17:18:09 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id C0E326128D for ; Mon, 24 May 2021 17:18:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C0E326128D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 51E254B148; Mon, 24 May 2021 13:18:08 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RGRgbqXaUusL; Mon, 24 May 2021 13:18:06 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 947F94B14E; Mon, 24 May 2021 13:18:06 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6A15C4B147 for ; Mon, 24 May 2021 13:18:05 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xIw8qK6dQI4K for ; Mon, 24 May 2021 13:18:04 -0400 (EDT) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 1B4034A483 for ; Mon, 24 May 2021 13:18:04 -0400 (EDT) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 54AD5610A6; Mon, 24 May 2021 17:18:02 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1llEDI-003Ifj-8k; Mon, 24 May 2021 18:18:00 +0100 Date: Mon, 24 May 2021 18:17:59 +0100 Message-ID: <87cztgvyns.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Subject: Re: [PATCH v3 4/9] KVM: arm64: vgic: Let an interrupt controller advertise lack of HW deactivation In-Reply-To: <417846b3-ff5e-1832-82b2-3e0064275944@arm.com> References: <20210510134824.1910399-1-maz@kernel.org> <20210510134824.1910399-5-maz@kernel.org> <417846b3-ff5e-1832-82b2-3e0064275944@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, james.morse@arm.com, suzuki.poulose@arm.com, eric.auger@redhat.com, marcan@marcan.st, mark.rutland@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, Hector Martin , kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Alex, On Fri, 21 May 2021 18:01:05 +0100, Alexandru Elisei wrote: > > Hi Marc, > > On 5/10/21 2:48 PM, Marc Zyngier wrote: > > The vGIC, as architected by ARM, allows a virtual interrupt to > > trigger the deactivation of a physical interrupt. This allows > > the following interrupt to be delivered without requiring an exit. > > If I got this right, the AIC doesn't implement/ignores the s/AIC/M1 CPU/ > ICH_LR_EL2.HW bit. Does it mean that the CPU IF behaves as if HW = > 0b0, meaning it asserts a maintenance interrupt on virtual interrupt > deactivation when ICH_LR_EL2.EOI = 0b1? I assume that's the case, > just double checking. Yes, that's what it looks like. > I am wondering what would happen if we come across an interrupt > controller where the CPU IF cannot assert a maintenance interrupt at > all and we rely on the EOI bit to take us out of the guest to > deactivate the HW interrupt. That'd be broken, and we wouldn't be able to support such an implementation, at least not in configuration such as CPU isolation. > I have to say that it looks a bit strange to start relying on the > maintenance interrupt to emulate interrupt deactivate for hardware > interrupts, but at the same timer allowing an interrupt controller > without a maintenance interrupt. We are not allowing a vGIC without a maintenance interrupt. We are actively mandating it. The M1 does have a working per-CPU maintenance interrupt. It just isn't wired into an interrupt controller, which means we can't mask it. But it is otherwise perfectly functional. > Other than that, this idea sounds like the best thing to do > considering the circumstances, I certainly can't think of anything > better. > > > > > However, some implementations have choosen not to implement this, > > meaning that we will need some unsavoury workarounds to deal with this. > > > > On detecting such a case, taint the kernel and spit a nastygram. > > We'll deal with this in later patches. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/vgic/vgic-init.c | 10 ++++++++++ > > include/kvm/arm_vgic.h | 3 +++ > > include/linux/irqchip/arm-vgic-info.h | 2 ++ > > 3 files changed, 15 insertions(+) > > > > diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c > > index 9fd23f32aa54..5b06a9970a57 100644 > > --- a/arch/arm64/kvm/vgic/vgic-init.c > > +++ b/arch/arm64/kvm/vgic/vgic-init.c > > @@ -524,6 +524,16 @@ int kvm_vgic_hyp_init(void) > > if (!gic_kvm_info) > > return -ENODEV; > > > > + /* > > + * If we get one of these oddball non-GICs, taint the kernel, > > + * as we have no idea of how they *really* behave. > > + */ > > + if (gic_kvm_info->no_hw_deactivation) { > > + kvm_info("Non-architectural vgic, tainting kernel\n"); > > + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); > > + kvm_vgic_global_state.no_hw_deactivation = true; > > + } > > IMO, since this means we're going to rely even more on the > maintenance interrupt (not just for software emulation of level > sensitive interrupts), I think there should be some sort of > dependency on having something that resembles a working maintenance > interrupt. But the timer interrupt is exactly a SW emulation of a level sensitive interrupt in this context. And the maintenance interrupt is still required to use the vGIC. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E51A0C2B9F7 for ; Tue, 25 May 2021 00:36:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AACE46141C for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llL0k-002ZwU-Kf; Tue, 25 May 2021 00:33:31 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1llEDK-001FHu-On for linux-arm-kernel@lists.infradead.org; Mon, 24 May 2021 17:18:04 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 54AD5610A6; Mon, 24 May 2021 17:18:02 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1llEDI-003Ifj-8k; Mon, 24 May 2021 18:18:00 +0100 Date: Mon, 24 May 2021 18:17:59 +0100 Message-ID: <87cztgvyns.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, James Morse , Suzuki K Poulose , Eric Auger , Hector Martin , Mark Rutland , kernel-team@android.com Subject: Re: [PATCH v3 4/9] KVM: arm64: vgic: Let an interrupt controller advertise lack of HW deactivation In-Reply-To: <417846b3-ff5e-1832-82b2-3e0064275944@arm.com> References: <20210510134824.1910399-1-maz@kernel.org> <20210510134824.1910399-5-maz@kernel.org> <417846b3-ff5e-1832-82b2-3e0064275944@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, james.morse@arm.com, suzuki.poulose@arm.com, eric.auger@redhat.com, marcan@marcan.st, mark.rutland@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_101802_885320_AF527D89 X-CRM114-Status: GOOD ( 40.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Alex, On Fri, 21 May 2021 18:01:05 +0100, Alexandru Elisei wrote: > > Hi Marc, > > On 5/10/21 2:48 PM, Marc Zyngier wrote: > > The vGIC, as architected by ARM, allows a virtual interrupt to > > trigger the deactivation of a physical interrupt. This allows > > the following interrupt to be delivered without requiring an exit. > > If I got this right, the AIC doesn't implement/ignores the s/AIC/M1 CPU/ > ICH_LR_EL2.HW bit. Does it mean that the CPU IF behaves as if HW = > 0b0, meaning it asserts a maintenance interrupt on virtual interrupt > deactivation when ICH_LR_EL2.EOI = 0b1? I assume that's the case, > just double checking. Yes, that's what it looks like. > I am wondering what would happen if we come across an interrupt > controller where the CPU IF cannot assert a maintenance interrupt at > all and we rely on the EOI bit to take us out of the guest to > deactivate the HW interrupt. That'd be broken, and we wouldn't be able to support such an implementation, at least not in configuration such as CPU isolation. > I have to say that it looks a bit strange to start relying on the > maintenance interrupt to emulate interrupt deactivate for hardware > interrupts, but at the same timer allowing an interrupt controller > without a maintenance interrupt. We are not allowing a vGIC without a maintenance interrupt. We are actively mandating it. The M1 does have a working per-CPU maintenance interrupt. It just isn't wired into an interrupt controller, which means we can't mask it. But it is otherwise perfectly functional. > Other than that, this idea sounds like the best thing to do > considering the circumstances, I certainly can't think of anything > better. > > > > > However, some implementations have choosen not to implement this, > > meaning that we will need some unsavoury workarounds to deal with this. > > > > On detecting such a case, taint the kernel and spit a nastygram. > > We'll deal with this in later patches. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/vgic/vgic-init.c | 10 ++++++++++ > > include/kvm/arm_vgic.h | 3 +++ > > include/linux/irqchip/arm-vgic-info.h | 2 ++ > > 3 files changed, 15 insertions(+) > > > > diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c > > index 9fd23f32aa54..5b06a9970a57 100644 > > --- a/arch/arm64/kvm/vgic/vgic-init.c > > +++ b/arch/arm64/kvm/vgic/vgic-init.c > > @@ -524,6 +524,16 @@ int kvm_vgic_hyp_init(void) > > if (!gic_kvm_info) > > return -ENODEV; > > > > + /* > > + * If we get one of these oddball non-GICs, taint the kernel, > > + * as we have no idea of how they *really* behave. > > + */ > > + if (gic_kvm_info->no_hw_deactivation) { > > + kvm_info("Non-architectural vgic, tainting kernel\n"); > > + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); > > + kvm_vgic_global_state.no_hw_deactivation = true; > > + } > > IMO, since this means we're going to rely even more on the > maintenance interrupt (not just for software emulation of level > sensitive interrupts), I think there should be some sort of > dependency on having something that resembles a working maintenance > interrupt. But the timer interrupt is exactly a SW emulation of a level sensitive interrupt in this context. And the maintenance interrupt is still required to use the vGIC. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel