From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: sw@weilnetz.de, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 29/93] tcg/tci: Remove TCG_CONST
Date: Thu, 04 Feb 2021 15:39:22 +0000 [thread overview]
Message-ID: <87czxfq1t0.fsf@linaro.org> (raw)
In-Reply-To: <20210204014509.882821-30-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> Only allow registers or constants, but not both, in any
> given position.
Aren't we switching to all registers (there are no more _i functions
after this)? I guess you mean the registers can have constants in them?
> Removing this difference in input will
> allow more code to be shared between 32-bit and 64-bit.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tci/tcg-target-con-set.h | 6 +-
> tcg/tci/tcg-target.h | 3 -
> tcg/tci.c | 189 +++++++++++++----------------------
> tcg/tci/tcg-target.c.inc | 82 ++++-----------
> 4 files changed, 89 insertions(+), 191 deletions(-)
>
> diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h
> index 38e82f7535..f51b7bcb13 100644
> --- a/tcg/tci/tcg-target-con-set.h
> +++ b/tcg/tci/tcg-target-con-set.h
> @@ -10,16 +10,12 @@
> * tcg-target-con-str.h; the constraint combination is inclusive or.
> */
> C_O0_I2(r, r)
> -C_O0_I2(r, ri)
> C_O0_I3(r, r, r)
> -C_O0_I4(r, r, ri, ri)
> C_O0_I4(r, r, r, r)
> C_O1_I1(r, r)
> C_O1_I2(r, 0, r)
> -C_O1_I2(r, ri, ri)
> C_O1_I2(r, r, r)
> -C_O1_I2(r, r, ri)
> -C_O1_I4(r, r, r, ri, ri)
> +C_O1_I4(r, r, r, r, r)
> C_O2_I1(r, r, r)
> C_O2_I2(r, r, r, r)
> C_O2_I4(r, r, r, r, r, r)
> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
> index 8f7ed676fc..9c0021a26f 100644
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -157,9 +157,6 @@ typedef enum {
>
> TCG_AREG0 = TCG_REG_R14,
> TCG_REG_CALL_STACK = TCG_REG_R15,
> -
> - /* Special value UINT8_MAX is used by TCI to encode constant values. */
> - TCG_CONST = UINT8_MAX
> } TCGReg;
>
> /* Used for function call generation. */
> diff --git a/tcg/tci.c b/tcg/tci.c
> index 935eb87330..fb3c97aaf1 100644
> --- a/tcg/tci.c
> +++ b/tcg/tci.c
> @@ -255,61 +255,6 @@ tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
> return taddr;
> }
>
> -/* Read indexed register or constant (native size) from bytecode. */
> -static tcg_target_ulong
> -tci_read_ri(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
> -{
> - tcg_target_ulong value;
> - TCGReg r = **tb_ptr;
> - *tb_ptr += 1;
> - if (r == TCG_CONST) {
> - value = tci_read_i(tb_ptr);
> - } else {
> - value = tci_read_reg(regs, r);
> - }
> - return value;
> -}
> -
> -/* Read indexed register or constant (32 bit) from bytecode. */
> -static uint32_t tci_read_ri32(const tcg_target_ulong *regs,
> - const uint8_t **tb_ptr)
> -{
> - uint32_t value;
> - TCGReg r = **tb_ptr;
> - *tb_ptr += 1;
> - if (r == TCG_CONST) {
> - value = tci_read_i32(tb_ptr);
> - } else {
> - value = tci_read_reg32(regs, r);
> - }
> - return value;
> -}
> -
> -#if TCG_TARGET_REG_BITS == 32
> -/* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
> -static uint64_t tci_read_ri64(const tcg_target_ulong *regs,
> - const uint8_t **tb_ptr)
> -{
> - uint32_t low = tci_read_ri32(regs, tb_ptr);
> - return tci_uint64(tci_read_ri32(regs, tb_ptr), low);
> -}
> -#elif TCG_TARGET_REG_BITS == 64
> -/* Read indexed register or constant (64 bit) from bytecode. */
> -static uint64_t tci_read_ri64(const tcg_target_ulong *regs,
> - const uint8_t **tb_ptr)
> -{
> - uint64_t value;
> - TCGReg r = **tb_ptr;
> - *tb_ptr += 1;
> - if (r == TCG_CONST) {
> - value = tci_read_i64(tb_ptr);
> - } else {
> - value = tci_read_reg64(regs, r);
> - }
> - return value;
> -}
> -#endif
> -
> static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr)
> {
> tcg_target_ulong label = tci_read_i(tb_ptr);
> @@ -504,7 +449,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
>
> switch (opc) {
> case INDEX_op_call:
> - t0 = tci_read_ri(regs, &tb_ptr);
> + t0 = tci_read_i(&tb_ptr);
> tci_tb_ptr = (uintptr_t)tb_ptr;
> #if TCG_TARGET_REG_BITS == 32
> tmp64 = ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0),
> @@ -539,7 +484,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> case INDEX_op_setcond_i32:
> t0 = *tb_ptr++;
> t1 = tci_read_r32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> condition = *tb_ptr++;
> tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
> break;
> @@ -547,7 +492,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> case INDEX_op_setcond2_i32:
> t0 = *tb_ptr++;
> tmp64 = tci_read_r64(regs, &tb_ptr);
> - v64 = tci_read_ri64(regs, &tb_ptr);
> + v64 = tci_read_r64(regs, &tb_ptr);
> condition = *tb_ptr++;
> tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition));
> break;
> @@ -555,7 +500,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> case INDEX_op_setcond_i64:
> t0 = *tb_ptr++;
> t1 = tci_read_r64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> condition = *tb_ptr++;
> tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
> break;
> @@ -628,62 +573,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
>
> case INDEX_op_add_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 + t2);
> break;
> case INDEX_op_sub_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 - t2);
> break;
> case INDEX_op_mul_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 * t2);
> break;
> case INDEX_op_div_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
> break;
> case INDEX_op_divu_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 / t2);
> break;
> case INDEX_op_rem_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
> break;
> case INDEX_op_remu_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 % t2);
> break;
> case INDEX_op_and_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 & t2);
> break;
> case INDEX_op_or_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 | t2);
> break;
> case INDEX_op_xor_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 ^ t2);
> break;
>
> @@ -691,33 +636,33 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
>
> case INDEX_op_shl_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 << (t2 & 31));
> break;
> case INDEX_op_shr_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 >> (t2 & 31));
> break;
> case INDEX_op_sar_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31)));
> break;
> #if TCG_TARGET_HAS_rot_i32
> case INDEX_op_rotl_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, rol32(t1, t2 & 31));
> break;
> case INDEX_op_rotr_i32:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri32(regs, &tb_ptr);
> - t2 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> + t2 = tci_read_r32(regs, &tb_ptr);
> tci_write_reg(regs, t0, ror32(t1, t2 & 31));
> break;
> #endif
> @@ -734,7 +679,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> #endif
> case INDEX_op_brcond_i32:
> t0 = tci_read_r32(regs, &tb_ptr);
> - t1 = tci_read_ri32(regs, &tb_ptr);
> + t1 = tci_read_r32(regs, &tb_ptr);
> condition = *tb_ptr++;
> label = tci_read_label(&tb_ptr);
> if (tci_compare32(t0, t1, condition)) {
> @@ -760,7 +705,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> break;
> case INDEX_op_brcond2_i32:
> tmp64 = tci_read_r64(regs, &tb_ptr);
> - v64 = tci_read_ri64(regs, &tb_ptr);
> + v64 = tci_read_r64(regs, &tb_ptr);
> condition = *tb_ptr++;
> label = tci_read_label(&tb_ptr);
> if (tci_compare64(tmp64, v64, condition)) {
> @@ -870,62 +815,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
>
> case INDEX_op_add_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 + t2);
> break;
> case INDEX_op_sub_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 - t2);
> break;
> case INDEX_op_mul_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 * t2);
> break;
> case INDEX_op_div_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
> break;
> case INDEX_op_divu_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
> break;
> case INDEX_op_rem_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
> break;
> case INDEX_op_remu_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
> break;
> case INDEX_op_and_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 & t2);
> break;
> case INDEX_op_or_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 | t2);
> break;
> case INDEX_op_xor_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 ^ t2);
> break;
>
> @@ -933,33 +878,33 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
>
> case INDEX_op_shl_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 << (t2 & 63));
> break;
> case INDEX_op_shr_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, t1 >> (t2 & 63));
> break;
> case INDEX_op_sar_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
> break;
> #if TCG_TARGET_HAS_rot_i64
> case INDEX_op_rotl_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, rol64(t1, t2 & 63));
> break;
> case INDEX_op_rotr_i64:
> t0 = *tb_ptr++;
> - t1 = tci_read_ri64(regs, &tb_ptr);
> - t2 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> + t2 = tci_read_r64(regs, &tb_ptr);
> tci_write_reg(regs, t0, ror64(t1, t2 & 63));
> break;
> #endif
> @@ -976,7 +921,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
> #endif
> case INDEX_op_brcond_i64:
> t0 = tci_read_r64(regs, &tb_ptr);
> - t1 = tci_read_ri64(regs, &tb_ptr);
> + t1 = tci_read_r64(regs, &tb_ptr);
> condition = *tb_ptr++;
> label = tci_read_label(&tb_ptr);
> if (tci_compare64(t0, t1, condition)) {
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index 1b66368c94..feac4659cc 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -92,8 +92,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
> case INDEX_op_rem_i64:
> case INDEX_op_remu_i32:
> case INDEX_op_remu_i64:
> - return C_O1_I2(r, r, r);
> -
> case INDEX_op_add_i32:
> case INDEX_op_add_i64:
> case INDEX_op_sub_i32:
> @@ -126,8 +124,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
> case INDEX_op_rotl_i64:
> case INDEX_op_rotr_i32:
> case INDEX_op_rotr_i64:
> - /* TODO: Does R, RI, RI result in faster code than R, R, RI? */
> - return C_O1_I2(r, ri, ri);
> + case INDEX_op_setcond_i32:
> + case INDEX_op_setcond_i64:
> + return C_O1_I2(r, r, r);
>
> case INDEX_op_deposit_i32:
> case INDEX_op_deposit_i64:
> @@ -135,11 +134,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
>
> case INDEX_op_brcond_i32:
> case INDEX_op_brcond_i64:
> - return C_O0_I2(r, ri);
> -
> - case INDEX_op_setcond_i32:
> - case INDEX_op_setcond_i64:
> - return C_O1_I2(r, r, ri);
> + return C_O0_I2(r, r);
>
> #if TCG_TARGET_REG_BITS == 32
> /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
> @@ -147,11 +142,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
> case INDEX_op_sub2_i32:
> return C_O2_I4(r, r, r, r, r, r);
> case INDEX_op_brcond2_i32:
> - return C_O0_I4(r, r, ri, ri);
> + return C_O0_I4(r, r, r, r);
> case INDEX_op_mulu2_i32:
> return C_O2_I2(r, r, r, r);
> case INDEX_op_setcond2_i32:
> - return C_O1_I4(r, r, r, ri, ri);
> + return C_O1_I4(r, r, r, r, r);
> #endif
>
> case INDEX_op_qemu_ld_i32:
> @@ -294,41 +289,6 @@ static void tcg_out_r(TCGContext *s, TCGArg t0)
> tcg_out8(s, t0);
> }
>
> -/* Write register or constant (native size). */
> -static void tcg_out_ri(TCGContext *s, bool const_arg, TCGArg arg)
> -{
> - if (const_arg) {
> - tcg_out8(s, TCG_CONST);
> - tcg_out_i(s, arg);
> - } else {
> - tcg_out_r(s, arg);
> - }
> -}
> -
> -/* Write register or constant (32 bit). */
> -static void tcg_out_ri32(TCGContext *s, bool const_arg, TCGArg arg)
> -{
> - if (const_arg) {
> - tcg_out8(s, TCG_CONST);
> - tcg_out32(s, arg);
> - } else {
> - tcg_out_r(s, arg);
> - }
> -}
> -
> -#if TCG_TARGET_REG_BITS == 64
> -/* Write register or constant (64 bit). */
> -static void tcg_out_ri64(TCGContext *s, bool const_arg, TCGArg arg)
> -{
> - if (const_arg) {
> - tcg_out8(s, TCG_CONST);
> - tcg_out64(s, arg);
> - } else {
> - tcg_out_r(s, arg);
> - }
> -}
> -#endif
> -
> /* Write label. */
> static void tci_out_label(TCGContext *s, TCGLabel *label)
> {
> @@ -416,7 +376,7 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
> {
> uint8_t *old_code_ptr = s->code_ptr;
> tcg_out_op_t(s, INDEX_op_call);
> - tcg_out_ri(s, 1, (uintptr_t)arg);
> + tcg_out_i(s, (uintptr_t)arg);
> old_code_ptr[1] = s->code_ptr - old_code_ptr;
> }
>
> @@ -450,7 +410,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> case INDEX_op_setcond_i32:
> tcg_out_r(s, args[0]);
> tcg_out_r(s, args[1]);
> - tcg_out_ri32(s, const_args[2], args[2]);
> + tcg_out_r(s, args[2]);
> tcg_out8(s, args[3]); /* condition */
> break;
> #if TCG_TARGET_REG_BITS == 32
> @@ -459,15 +419,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> tcg_out_r(s, args[0]);
> tcg_out_r(s, args[1]);
> tcg_out_r(s, args[2]);
> - tcg_out_ri32(s, const_args[3], args[3]);
> - tcg_out_ri32(s, const_args[4], args[4]);
> + tcg_out_r(s, args[3]);
> + tcg_out_r(s, args[4]);
> tcg_out8(s, args[5]); /* condition */
> break;
> #elif TCG_TARGET_REG_BITS == 64
> case INDEX_op_setcond_i64:
> tcg_out_r(s, args[0]);
> tcg_out_r(s, args[1]);
> - tcg_out_ri64(s, const_args[2], args[2]);
> + tcg_out_r(s, args[2]);
> tcg_out8(s, args[3]); /* condition */
> break;
> #endif
> @@ -513,8 +473,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
> case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
> tcg_out_r(s, args[0]);
> - tcg_out_ri32(s, const_args[1], args[1]);
> - tcg_out_ri32(s, const_args[2], args[2]);
> + tcg_out_r(s, args[1]);
> + tcg_out_r(s, args[2]);
> break;
> case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */
> tcg_out_r(s, args[0]);
> @@ -548,8 +508,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
> case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
> tcg_out_r(s, args[0]);
> - tcg_out_ri64(s, const_args[1], args[1]);
> - tcg_out_ri64(s, const_args[2], args[2]);
> + tcg_out_r(s, args[1]);
> + tcg_out_r(s, args[2]);
> break;
> case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
> tcg_out_r(s, args[0]);
> @@ -562,7 +522,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> break;
> case INDEX_op_brcond_i64:
> tcg_out_r(s, args[0]);
> - tcg_out_ri64(s, const_args[1], args[1]);
> + tcg_out_r(s, args[1]);
> tcg_out8(s, args[2]); /* condition */
> tci_out_label(s, arg_label(args[3]));
> break;
> @@ -596,8 +556,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
> case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
> tcg_out_r(s, args[0]);
> - tcg_out_ri32(s, const_args[1], args[1]);
> - tcg_out_ri32(s, const_args[2], args[2]);
> + tcg_out_r(s, args[1]);
> + tcg_out_r(s, args[2]);
> break;
> #if TCG_TARGET_REG_BITS == 32
> case INDEX_op_add2_i32:
> @@ -612,8 +572,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> case INDEX_op_brcond2_i32:
> tcg_out_r(s, args[0]);
> tcg_out_r(s, args[1]);
> - tcg_out_ri32(s, const_args[2], args[2]);
> - tcg_out_ri32(s, const_args[3], args[3]);
> + tcg_out_r(s, args[2]);
> + tcg_out_r(s, args[3]);
> tcg_out8(s, args[4]); /* condition */
> tci_out_label(s, arg_label(args[5]));
> break;
> @@ -626,7 +586,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> #endif
> case INDEX_op_brcond_i32:
> tcg_out_r(s, args[0]);
> - tcg_out_ri32(s, const_args[1], args[1]);
> + tcg_out_r(s, args[1]);
> tcg_out8(s, args[2]); /* condition */
> tci_out_label(s, arg_label(args[3]));
> break;
--
Alex Bennée
next prev parent reply other threads:[~2021-02-04 15:46 UTC|newest]
Thread overview: 129+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-04 1:43 [PATCH v2 00/93] TCI fixes and cleanups Richard Henderson
2021-02-04 1:43 ` [PATCH v2 01/93] gdbstub: Fix handle_query_xfer_auxv Richard Henderson
2021-02-04 1:43 ` [PATCH v2 02/93] tcg: Split out tcg_raise_tb_overflow Richard Henderson
2021-02-04 1:43 ` [PATCH v2 03/93] configure: Fix --enable-tcg-interpreter Richard Henderson
2021-02-04 1:43 ` [PATCH v2 04/93] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Richard Henderson
2021-02-04 15:01 ` Alex Bennée
2021-02-04 17:46 ` Richard Henderson
2021-02-04 18:45 ` Alex Bennée
2021-02-04 19:17 ` Richard Henderson
2021-02-04 1:43 ` [PATCH v2 05/93] tcg/tci: Make tci_tb_ptr thread-local Richard Henderson
2021-02-04 15:05 ` Alex Bennée
2021-02-04 1:43 ` [PATCH v2 06/93] tcg/tci: Implement INDEX_op_ld16s_i32 Richard Henderson
2021-02-04 1:43 ` [PATCH v2 07/93] tcg/tci: Implement INDEX_op_ld8s_i64 Richard Henderson
2021-02-04 1:43 ` [PATCH v2 08/93] tcg/tci: Inline tci_write_reg32s into the only caller Richard Henderson
2021-02-04 1:43 ` [PATCH v2 09/93] tcg/tci: Inline tci_write_reg8 into its callers Richard Henderson
2021-02-04 1:43 ` [PATCH v2 10/93] tcg/tci: Inline tci_write_reg16 into the only caller Richard Henderson
2021-02-04 1:43 ` [PATCH v2 11/93] tcg/tci: Inline tci_write_reg32 into all callers Richard Henderson
2021-02-04 1:43 ` [PATCH v2 12/93] tcg/tci: Inline tci_write_reg64 into 64-bit callers Richard Henderson
2021-02-04 1:43 ` [PATCH v2 13/93] tcg/tci: Merge INDEX_op_ld8u_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 14/93] tcg/tci: Merge INDEX_op_ld8s_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 15/93] tcg/tci: Merge INDEX_op_ld16u_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 16/93] tcg/tci: Merge INDEX_op_ld16s_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 17/93] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 18/93] tcg/tci: Merge INDEX_op_st8_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 19/93] tcg/tci: Merge INDEX_op_st16_{i32,i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 20/93] tcg/tci: Move stack bounds check to compile-time Richard Henderson
2021-02-04 1:43 ` [PATCH v2 21/93] tcg/tci: Merge INDEX_op_{st_i32,st32_i64} Richard Henderson
2021-02-04 1:43 ` [PATCH v2 22/93] tcg/tci: Use g_assert_not_reached Richard Henderson
2021-02-04 1:43 ` [PATCH v2 23/93] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_* Richard Henderson
2021-02-04 1:44 ` [PATCH v2 24/93] tcg/tci: Implement 64-bit division Richard Henderson
2021-02-04 1:44 ` [PATCH v2 25/93] tcg/tci: Remove TODO as unused Richard Henderson
2021-02-04 1:44 ` [PATCH v2 26/93] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16 Richard Henderson
2021-02-04 15:07 ` Alex Bennée
2021-02-04 1:44 ` [PATCH v2 27/93] tcg/tci: Fix TCG_REG_R4 misusage Richard Henderson
2021-02-04 15:09 ` Alex Bennée
2021-02-04 1:44 ` [PATCH v2 28/93] tcg/tci: Use bool in tcg_out_ri* Richard Henderson
2021-02-04 15:11 ` Alex Bennée
2021-02-04 15:15 ` Alex Bennée
2021-02-04 1:44 ` [PATCH v2 29/93] tcg/tci: Remove TCG_CONST Richard Henderson
2021-02-04 15:39 ` Alex Bennée [this message]
2021-02-04 17:52 ` Richard Henderson
2021-02-04 18:48 ` Alex Bennée
2021-02-04 1:44 ` [PATCH v2 30/93] tcg/tci: Merge identical cases in generation Richard Henderson
2021-02-04 1:44 ` [PATCH v2 31/93] tcg/tci: Remove tci_read_r8 Richard Henderson
2021-02-04 1:44 ` [PATCH v2 32/93] tcg/tci: Remove tci_read_r8s Richard Henderson
2021-02-04 1:44 ` [PATCH v2 33/93] tcg/tci: Remove tci_read_r16 Richard Henderson
2021-02-04 1:44 ` [PATCH v2 34/93] tcg/tci: Remove tci_read_r16s Richard Henderson
2021-02-04 1:44 ` [PATCH v2 35/93] tcg/tci: Remove tci_read_r32s Richard Henderson
2021-02-04 1:44 ` [PATCH v2 36/93] tcg/tci: Reduce use of tci_read_r64 Richard Henderson
2021-02-04 1:44 ` [PATCH v2 37/93] tcg/tci: Merge basic arithmetic operations Richard Henderson
2021-02-04 1:44 ` [PATCH v2 38/93] tcg/tci: Merge extension operations Richard Henderson
2021-02-04 1:44 ` [PATCH v2 39/93] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
2021-02-04 1:44 ` [PATCH v2 40/93] tcg/tci: Merge bswap operations Richard Henderson
2021-02-04 1:44 ` [PATCH v2 41/93] tcg/tci: Merge mov, not and neg operations Richard Henderson
2021-02-04 1:44 ` [PATCH v2 42/93] tcg/tci: Rename tci_read_r to tci_read_rval Richard Henderson
2021-02-04 1:44 ` [PATCH v2 43/93] tcg/tci: Split out tci_args_rrs Richard Henderson
2021-02-04 1:44 ` [PATCH v2 44/93] tcg/tci: Split out tci_args_rr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 45/93] tcg/tci: Split out tci_args_rrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 46/93] tcg/tci: Split out tci_args_rrrc Richard Henderson
2021-02-04 1:44 ` [PATCH v2 47/93] tcg/tci: Split out tci_args_l Richard Henderson
2021-02-04 1:44 ` [PATCH v2 48/93] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
2021-02-04 1:44 ` [PATCH v2 49/93] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
2021-02-04 1:44 ` [PATCH v2 50/93] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
2021-02-04 1:44 ` [PATCH v2 51/93] tcg/tci: Reuse tci_args_l for calls Richard Henderson
2021-02-04 1:44 ` [PATCH v2 52/93] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
2021-02-04 1:44 ` [PATCH v2 53/93] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
2021-02-04 1:44 ` [PATCH v2 54/93] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 55/93] tcg/tci: Split out tci_args_rrrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 56/93] tcg/tci: Clean up deposit operations Richard Henderson
2021-02-04 1:44 ` [PATCH v2 57/93] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
2021-02-04 1:44 ` [PATCH v2 58/93] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-04 1:44 ` [PATCH v2 59/93] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
2021-02-04 1:44 ` [PATCH v2 60/93] tcg/tci: Remove tci_disas Richard Henderson
2021-02-04 1:44 ` [PATCH v2 61/93] tcg/tci: Implement the disassembler properly Richard Henderson
2021-02-04 1:44 ` [PATCH v2 62/93] tcg: Build ffi data structures for helpers Richard Henderson
2021-02-04 1:44 ` [PATCH v2 63/93] tcg/tci: Use ffi for calls Richard Henderson
2021-02-07 16:25 ` Stefan Weil
2021-02-07 17:39 ` Richard Henderson
2021-02-07 19:52 ` Peter Maydell
2021-02-07 20:12 ` Richard Henderson
2021-02-07 21:33 ` Stefan Weil
2021-02-08 9:20 ` Peter Maydell
2021-02-08 9:35 ` Paolo Bonzini
2021-02-08 13:07 ` Stefan Weil
2021-02-08 17:39 ` Richard Henderson
2021-02-08 19:04 ` Stefan Weil
2021-02-08 22:55 ` Richard Henderson
2021-02-09 20:46 ` Richard Henderson
2021-02-09 21:15 ` Stefan Weil
2021-02-09 21:54 ` Stefan Weil
2021-02-04 1:44 ` [PATCH v2 64/93] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-02-04 1:44 ` [PATCH v2 65/93] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-02-04 1:44 ` [PATCH v2 66/93] tcg/tci: Push opcode emit into each case Richard Henderson
2021-02-04 1:44 ` [PATCH v2 67/93] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
2021-02-04 1:44 ` [PATCH v2 68/93] tcg/tci: Split out tcg_out_op_l Richard Henderson
2021-02-04 1:44 ` [PATCH v2 69/93] tcg/tci: Split out tcg_out_op_p Richard Henderson
2021-02-04 1:44 ` [PATCH v2 70/93] tcg/tci: Split out tcg_out_op_rr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 71/93] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 72/93] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
2021-02-04 1:44 ` [PATCH v2 73/93] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
2021-02-04 1:44 ` [PATCH v2 74/93] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
2021-02-04 1:44 ` [PATCH v2 75/93] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
2021-02-04 1:44 ` [PATCH v2 76/93] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 77/93] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
2021-02-04 1:44 ` [PATCH v2 78/93] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
2021-02-04 1:44 ` [PATCH v2 79/93] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-04 1:54 ` Richard Henderson
2021-02-04 14:54 ` Alex Bennée
2021-02-04 17:54 ` Richard Henderson
2021-02-04 1:54 ` [PATCH v2 80/93] tcg/tci: Split out tcg_out_op_v Richard Henderson
2021-02-04 1:55 ` [PATCH v2 81/93] tcg/tci: Split out tcg_out_op_np Richard Henderson
2021-02-04 1:55 ` [PATCH v2 82/93] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
2021-02-04 1:55 ` [PATCH v2 83/93] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-02-04 1:56 ` [PATCH v2 84/93] tcg/tci: Emit setcond before brcond Richard Henderson
2021-02-04 1:56 ` [PATCH v2 85/93] tcg/tci: Remove tci_write_reg Richard Henderson
2021-02-04 1:56 ` [PATCH v2 86/93] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-02-04 1:57 ` [PATCH v2 87/93] tcg/tci: Implement goto_ptr Richard Henderson
2021-02-04 1:57 ` [PATCH v2 88/93] tcg/tci: Implement movcond Richard Henderson
2021-02-04 1:57 ` [PATCH v2 89/93] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-02-04 1:57 ` [PATCH v2 90/93] tcg/tci: Implement extract, sextract Richard Henderson
2021-02-04 1:58 ` [PATCH v2 91/93] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-02-04 1:58 ` [PATCH v2 92/93] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-02-04 1:58 ` [PATCH v2 93/93] tcg/tci: Implement add2, sub2 Richard Henderson
2021-02-04 3:31 ` [PATCH v2 00/93] TCI fixes and cleanups no-reply
2021-02-04 9:58 ` Peter Maydell
2021-02-04 20:02 ` Stefan Weil
2021-02-04 20:42 ` Richard Henderson
2021-02-04 23:52 ` Richard Henderson
2021-02-05 2:39 ` Richard Henderson
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