From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D44DFC433E1 for ; Wed, 10 Jun 2020 12:27:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B01F8206F4 for ; Wed, 10 Jun 2020 12:27:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hnRHTdJr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729063AbgFJM1p (ORCPT ); Wed, 10 Jun 2020 08:27:45 -0400 Received: from esa6.microchip.iphmx.com ([216.71.154.253]:46310 "EHLO esa6.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728595AbgFJM1p (ORCPT ); Wed, 10 Jun 2020 08:27:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1591792064; x=1623328064; h=references:from:to:cc:subject:in-reply-to:date: message-id:mime-version; bh=QiFuJl1R5fgwI47VUdUxy1XjRtgrcDqvma+iH44NFSk=; b=hnRHTdJronscFR2yTjdh97Lj7hS7DuvbTw98YNO51LZ3UXc/1VMvT8iB tL32XQg6qZmB6lfLXpoB2+hle/VHVqO0638F1CEGsBCKwtcezoAnTve40 UtUMcouuRqBCG2vZROnAdGnkLkF3n4xEH4so9O9shjaHuRwzWkSXN++Dg nAX7PHQHVJ+VPaqQzE/QaSkUOXkRjHN0YWkIxvvNbhEGsAoBZYHFFM+e1 XzF4NOtkHPx8N+c74t5M1N2DM2VmSRzs38MnZhCez0+lm1Ql7QT9DniJX /3Ff2ZGW35ZOcUDC3V/+4FNzDYCCEapg/1X7uBVSRMVOABLrnwaMGtED2 Q==; IronPort-SDR: 0d4g912uhVPOIXVwiNumUIxOuwQwPv1k6y8Nq0I/CzHL1DwOmpG02rnaDxCk0Xul9ey7Wz6RVN MoGmGnZ+EQRMel+AUBLPvkn7ON7+DX3N23NsBUbSe4kf82ZfGLZHOVKqaD2P/bCFZobnMwyTGW Mk/GSb29bEgBZO+qe3ATVlY/gWm3VEHHqjYkS8fUrMoicwslgxm0AquKfxlA4tXmFapYTg87ht IqeLuIZL/Xyzue7miwmvTsqASQip6ZlkRDLZm2sBWdIJbnx0uIdzdqdMkwOrhoL/map1dFX0IR qI4= X-IronPort-AV: E=Sophos;i="5.73,496,1583218800"; d="scan'208";a="15250796" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Jun 2020 05:27:36 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1847.3; Wed, 10 Jun 2020 05:27:35 -0700 Received: from soft-dev15.microsemi.net.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1847.3 via Frontend Transport; Wed, 10 Jun 2020 05:27:32 -0700 References: <20200513140031.25633-1-lars.povlsen@microchip.com> <20200513140031.25633-7-lars.povlsen@microchip.com> <20200602230738.mz2y6i2kjagyt7tk@mobilestation> From: Lars Povlsen To: Serge Semin List-Id: CC: Lars Povlsen , Serge Semin , Mark Brown , SoC Team , Rob Herring , , Alexandre Belloni , , , Microchip Linux Driver Support , Subject: Re: [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support In-Reply-To: <20200602230738.mz2y6i2kjagyt7tk@mobilestation> Date: Wed, 10 Jun 2020 14:27:31 +0200 Message-ID: <87d067hzrg.fsf@soft-dev15.microsemi.net> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Serge Semin writes: > On Wed, May 13, 2020 at 04:00:27PM +0200, Lars Povlsen wrote: >> This add DT bindings for the Sparx5 SPI driver. > > This whole file can be easily merged in to the generic DW APB SSI DT > binding file. Just use "if: properties: compatible: const: ..." construction > to distinguish ocelot, jaguar, sparx5 and non-sparx5 nodes. > >> >> Reviewed-by: Alexandre Belloni >> Signed-off-by: Lars Povlsen >> --- >> .../bindings/spi/mscc,ocelot-spi.yaml | 49 +++++++++++++++---- >> 1 file changed, 39 insertions(+), 10 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> index a3ac0fa576553..8beecde4b0880 100644 >> --- a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> @@ -23,15 +23,23 @@ properties: >> enum: >> - mscc,ocelot-spi >> - mscc,jaguar2-spi >> + - microchip,sparx5-spi >> >> interrupts: >> maxItems: 1 >> >> reg: >> minItems: 2 >> - items: >> - - description: Designware SPI registers >> - - description: CS override registers >> + maxItems: 3 >> + oneOf: >> + - items: >> + - description: Designware SPI registers >> + - description: CS override registers (Not sparx5). >> + - items: >> + - description: Designware SPI registers >> + - description: CS override registers (Not sparx5). >> + - description: Direct mapped SPI read area. If provided, the >> + driver will register spi_mem_op's to take advantage of it. >> >> clocks: >> maxItems: 1 >> @@ -43,6 +51,23 @@ properties: >> enum: [ 2, 4 ] >> maxItems: 1 >> > >> + spi-rx-delay-us: >> + description: | >> + The delay (in usec) of the RX signal sample position. This can >> + be used to tne the RX timing in order to acheive higher >> + speeds. This is used for all devices on the bus. >> + default: 0 >> + maxItems: 1 > > spi-rx-delay-us is defined for a particular SPI-slave. Please see the > DT binding file: Documentation/devicetree/bindings/spi/spi-controller.yaml . > Although as I suggested before this delay isn't what the Dw APB SSI RX sample > delay functionality does. Probably a vendor-specific property would be better > here. But I'd also define it on a SPI-slave basis, not for all devices on the > bus. Right, I was hunting for something "similar". As pointed out, this is really different in nature, and the unit is also too coarse. I will change this to "snps,rx-sample-delay-ns" as suggested in your other comments. > >> + >> + interface-mapping-mask: >> + description: | >> + On the Sparx5 variant, two different busses are connected to the >> + controller. This property is a mask per chip-select, indicating >> + whether the CS should go to one or the other interface. >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + default: 0 >> + maxItems: 1 > > As Mark rightfully suggested this seems like an SPI-slave related property, then > most likely it should be defined on the SPI-slave basis (probably as a bool > property). Additionally it's vendor-specific, so the property name should be > accordingly prefixed. Yes, I'll change this to a per-device property. I need the same for the above as well. > >> + >> required: >> - compatible >> - reg >> @@ -50,11 +75,15 @@ required: >> >> examples: >> - | >> - spi0: spi@101000 { >> - compatible = "mscc,ocelot-spi"; >> - #address-cells = <1>; >> - #size-cells = <0>; >> - reg = <0x101000 0x100>, <0x3c 0x18>; >> - interrupts = <9>; >> - clocks = <&ahb_clk>; >> + #include >> + spi0: spi@600104000 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "microchip,sparx5-spi"; > >> + reg = <0x00104000 0x40>, <0 0>, <0x3000000 0x4000000>; > > I have a doubt that defining an empty reg region is a good idea, since you can > detect the reg requirements by the node compatible string. Yes, its probably better that way. It looks ugly too :-) Thanks for your comments! ---Lars > -Sergey > >> + num-cs = <16>; >> + reg-io-width = <4>; >> + reg-shift = <2>; >> + clocks = <&ahb_clk>; >> + interrupts = ; >> }; >> -- >> 2.26.2 >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Lars Povlsen, Microchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A2BCC433E0 for ; Wed, 10 Jun 2020 12:27:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6C4F6206F4 for ; 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Wed, 10 Jun 2020 05:27:35 -0700 Received: from soft-dev15.microsemi.net.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1847.3 via Frontend Transport; Wed, 10 Jun 2020 05:27:32 -0700 References: <20200513140031.25633-1-lars.povlsen@microchip.com> <20200513140031.25633-7-lars.povlsen@microchip.com> <20200602230738.mz2y6i2kjagyt7tk@mobilestation> From: Lars Povlsen To: Serge Semin Subject: Re: [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support In-Reply-To: <20200602230738.mz2y6i2kjagyt7tk@mobilestation> Date: Wed, 10 Jun 2020 14:27:31 +0200 Message-ID: <87d067hzrg.fsf@soft-dev15.microsemi.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200610_052744_938913_77221045 X-CRM114-Status: GOOD ( 20.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , List-Id: Cc: devicetree@vger.kernel.org, Alexandre Belloni , Mark Brown , linux-kernel@vger.kernel.org, Serge Semin , linux-spi@vger.kernel.org, SoC Team , Rob Herring , linux-arm-kernel@lists.infradead.org, Microchip Linux Driver Support , Lars Povlsen Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Serge Semin writes: > On Wed, May 13, 2020 at 04:00:27PM +0200, Lars Povlsen wrote: >> This add DT bindings for the Sparx5 SPI driver. > > This whole file can be easily merged in to the generic DW APB SSI DT > binding file. Just use "if: properties: compatible: const: ..." construction > to distinguish ocelot, jaguar, sparx5 and non-sparx5 nodes. > >> >> Reviewed-by: Alexandre Belloni >> Signed-off-by: Lars Povlsen >> --- >> .../bindings/spi/mscc,ocelot-spi.yaml | 49 +++++++++++++++---- >> 1 file changed, 39 insertions(+), 10 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> index a3ac0fa576553..8beecde4b0880 100644 >> --- a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml >> @@ -23,15 +23,23 @@ properties: >> enum: >> - mscc,ocelot-spi >> - mscc,jaguar2-spi >> + - microchip,sparx5-spi >> >> interrupts: >> maxItems: 1 >> >> reg: >> minItems: 2 >> - items: >> - - description: Designware SPI registers >> - - description: CS override registers >> + maxItems: 3 >> + oneOf: >> + - items: >> + - description: Designware SPI registers >> + - description: CS override registers (Not sparx5). >> + - items: >> + - description: Designware SPI registers >> + - description: CS override registers (Not sparx5). >> + - description: Direct mapped SPI read area. If provided, the >> + driver will register spi_mem_op's to take advantage of it. >> >> clocks: >> maxItems: 1 >> @@ -43,6 +51,23 @@ properties: >> enum: [ 2, 4 ] >> maxItems: 1 >> > >> + spi-rx-delay-us: >> + description: | >> + The delay (in usec) of the RX signal sample position. This can >> + be used to tne the RX timing in order to acheive higher >> + speeds. This is used for all devices on the bus. >> + default: 0 >> + maxItems: 1 > > spi-rx-delay-us is defined for a particular SPI-slave. Please see the > DT binding file: Documentation/devicetree/bindings/spi/spi-controller.yaml . > Although as I suggested before this delay isn't what the Dw APB SSI RX sample > delay functionality does. Probably a vendor-specific property would be better > here. But I'd also define it on a SPI-slave basis, not for all devices on the > bus. Right, I was hunting for something "similar". As pointed out, this is really different in nature, and the unit is also too coarse. I will change this to "snps,rx-sample-delay-ns" as suggested in your other comments. > >> + >> + interface-mapping-mask: >> + description: | >> + On the Sparx5 variant, two different busses are connected to the >> + controller. This property is a mask per chip-select, indicating >> + whether the CS should go to one or the other interface. >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + default: 0 >> + maxItems: 1 > > As Mark rightfully suggested this seems like an SPI-slave related property, then > most likely it should be defined on the SPI-slave basis (probably as a bool > property). Additionally it's vendor-specific, so the property name should be > accordingly prefixed. Yes, I'll change this to a per-device property. I need the same for the above as well. > >> + >> required: >> - compatible >> - reg >> @@ -50,11 +75,15 @@ required: >> >> examples: >> - | >> - spi0: spi@101000 { >> - compatible = "mscc,ocelot-spi"; >> - #address-cells = <1>; >> - #size-cells = <0>; >> - reg = <0x101000 0x100>, <0x3c 0x18>; >> - interrupts = <9>; >> - clocks = <&ahb_clk>; >> + #include >> + spi0: spi@600104000 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "microchip,sparx5-spi"; > >> + reg = <0x00104000 0x40>, <0 0>, <0x3000000 0x4000000>; > > I have a doubt that defining an empty reg region is a good idea, since you can > detect the reg requirements by the node compatible string. Yes, its probably better that way. It looks ugly too :-) Thanks for your comments! ---Lars > -Sergey > >> + num-cs = <16>; >> + reg-io-width = <4>; >> + reg-shift = <2>; >> + clocks = <&ahb_clk>; >> + interrupts = ; >> }; >> -- >> 2.26.2 >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- Lars Povlsen, Microchip _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel