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Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Do not explicitly store zero to the NEON high part > when we can pass !is_q to clear_vec_high. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/translate-a64.c | 59 +++++++++++++++++++++++--------------- > 1 file changed, 36 insertions(+), 23 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index d57aa54d6a..bf82a2e115 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -948,11 +948,10 @@ static void do_fp_ld(DisasContext *s, int destidx, = TCGv_i64 tcg_addr, int size) > { > /* This always zero-extends and writes to a full 128 bit wide vector= */ > TCGv_i64 tmplo =3D tcg_temp_new_i64(); > - TCGv_i64 tmphi; > + TCGv_i64 tmphi =3D NULL; >=20=20 > if (size < 4) { > MemOp memop =3D s->be_data + size; > - tmphi =3D tcg_const_i64(0); > tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); > } else { > bool be =3D s->be_data =3D=3D MO_BE; > @@ -970,12 +969,13 @@ static void do_fp_ld(DisasContext *s, int destidx, = TCGv_i64 tcg_addr, int size) > } >=20=20 > tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); > - tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); > - > tcg_temp_free_i64(tmplo); > - tcg_temp_free_i64(tmphi); >=20=20 > - clear_vec_high(s, true, destidx); > + if (tmphi) { > + tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); > + tcg_temp_free_i64(tmphi); > + } > + clear_vec_high(s, tmphi !=3D NULL, destidx); > } >=20=20 > /* > @@ -6969,8 +6969,8 @@ static void disas_simd_ext(DisasContext *s, uint32_= t insn) > return; > } >=20=20 > - tcg_resh =3D tcg_temp_new_i64(); > tcg_resl =3D tcg_temp_new_i64(); > + tcg_resh =3D NULL; >=20=20 > /* Vd gets bits starting at pos bits into Vm:Vn. This is > * either extracting 128 bits from a 128:128 concatenation, or > @@ -6982,7 +6982,6 @@ static void disas_simd_ext(DisasContext *s, uint32_= t insn) > read_vec_element(s, tcg_resh, rm, 0, MO_64); > do_ext64(s, tcg_resh, tcg_resl, pos); > } > - tcg_gen_movi_i64(tcg_resh, 0); > } else { > TCGv_i64 tcg_hh; > typedef struct { > @@ -6997,6 +6996,7 @@ static void disas_simd_ext(DisasContext *s, uint32_= t insn) > pos -=3D 64; > } >=20=20 > + tcg_resh =3D tcg_temp_new_i64(); > read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); > elt++; > read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); > @@ -7012,9 +7012,12 @@ static void disas_simd_ext(DisasContext *s, uint32= _t insn) >=20=20 > write_vec_element(s, tcg_resl, rd, 0, MO_64); > tcg_temp_free_i64(tcg_resl); > - write_vec_element(s, tcg_resh, rd, 1, MO_64); > - tcg_temp_free_i64(tcg_resh); > - clear_vec_high(s, true, rd); > + > + if (is_q) { > + write_vec_element(s, tcg_resh, rd, 1, MO_64); > + tcg_temp_free_i64(tcg_resh); > + } > + clear_vec_high(s, is_q, rd); > } >=20=20 > /* TBL/TBX > @@ -7051,17 +7054,21 @@ static void disas_simd_tb(DisasContext *s, uint32= _t insn) > * the input. > */ > tcg_resl =3D tcg_temp_new_i64(); > - tcg_resh =3D tcg_temp_new_i64(); > + tcg_resh =3D NULL; >=20=20 > if (is_tblx) { > read_vec_element(s, tcg_resl, rd, 0, MO_64); > } else { > tcg_gen_movi_i64(tcg_resl, 0); > } > - if (is_tblx && is_q) { > - read_vec_element(s, tcg_resh, rd, 1, MO_64); > - } else { > - tcg_gen_movi_i64(tcg_resh, 0); > + > + if (is_q) { > + tcg_resh =3D tcg_temp_new_i64(); > + if (is_tblx) { > + read_vec_element(s, tcg_resh, rd, 1, MO_64); > + } else { > + tcg_gen_movi_i64(tcg_resh, 0); > + } > } >=20=20 > tcg_idx =3D tcg_temp_new_i64(); > @@ -7081,9 +7088,12 @@ static void disas_simd_tb(DisasContext *s, uint32_= t insn) >=20=20 > write_vec_element(s, tcg_resl, rd, 0, MO_64); > tcg_temp_free_i64(tcg_resl); > - write_vec_element(s, tcg_resh, rd, 1, MO_64); > - tcg_temp_free_i64(tcg_resh); > - clear_vec_high(s, true, rd); > + > + if (is_q) { > + write_vec_element(s, tcg_resh, rd, 1, MO_64); > + tcg_temp_free_i64(tcg_resh); > + } > + clear_vec_high(s, is_q, rd); > } >=20=20 > /* ZIP/UZP/TRN > @@ -7120,7 +7130,7 @@ static void disas_simd_zip_trn(DisasContext *s, uin= t32_t insn) > } >=20=20 > tcg_resl =3D tcg_const_i64(0); > - tcg_resh =3D tcg_const_i64(0); > + tcg_resh =3D is_q ? tcg_const_i64(0) : NULL; > tcg_res =3D tcg_temp_new_i64(); >=20=20 > for (i =3D 0; i < elements; i++) { > @@ -7171,9 +7181,12 @@ static void disas_simd_zip_trn(DisasContext *s, ui= nt32_t insn) >=20=20 > write_vec_element(s, tcg_resl, rd, 0, MO_64); > tcg_temp_free_i64(tcg_resl); > - write_vec_element(s, tcg_resh, rd, 1, MO_64); > - tcg_temp_free_i64(tcg_resh); > - clear_vec_high(s, true, rd); > + > + if (is_q) { > + write_vec_element(s, tcg_resh, rd, 1, MO_64); > + tcg_temp_free_i64(tcg_resh); > + } > + clear_vec_high(s, is_q, rd); > } >=20=20 > /* --=20 Alex Benn=C3=A9e