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X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , keithp@keithp.com, "open list:ARM TCG CPUs" , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > On 12/21/19 12:22 AM, Alex Benn=C3=A9e wrote: >> +#if defined(__arm__) >> + register uintptr_t t asm("r0") =3D type; >> + register uintptr_t a0 asm("r1") =3D arg0; >> + asm("svc 0xab" >> + : "=3Dr" (t) >> + : "r" (t), "r" (a0)); > > This is the #ifdef __thumb__ svc code. Are you enforcing that with > command-line arguments? No it is dealing with aarch64 vs 32 bit and the __arm__ is a compiler symbol.=20 > > Might as well fix this, then test both arm and thumb. I've enabled for Aarch64 just like the semihosting test. > > > r~ --=20 Alex Benn=C3=A9e