From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52396) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bP0s4-00032p-5z for qemu-devel@nongnu.org; Mon, 18 Jul 2016 01:13:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bP0s0-0003GY-Ok for qemu-devel@nongnu.org; Mon, 18 Jul 2016 01:13:35 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:34247) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bP0s0-0003GI-Er for qemu-devel@nongnu.org; Mon, 18 Jul 2016 01:13:32 -0400 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u6I4wPZX021076 for ; Mon, 18 Jul 2016 01:13:32 -0400 Received: from e23smtp02.au.ibm.com (e23smtp02.au.ibm.com [202.81.31.144]) by mx0a-001b2d01.pphosted.com with ESMTP id 24827ehj88-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 18 Jul 2016 01:13:31 -0400 Received: from localhost by e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 18 Jul 2016 15:13:28 +1000 From: Nikunj A Dadhania In-Reply-To: <20160718014858.GG16769@voom.fritz.box> References: <1468346602-20700-1-git-send-email-nikunj@linux.vnet.ibm.com> <1468346602-20700-2-git-send-email-nikunj@linux.vnet.ibm.com> <20160718014858.GG16769@voom.fritz.box> Date: Mon, 18 Jul 2016 10:43:15 +0530 MIME-Version: 1.0 Content-Type: text/plain Message-Id: <87d1mbplzo.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> Subject: Re: [Qemu-devel] [RFC 1/6] target-ppc: Introduce Power9 family List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, aneesh.kumar@linux.vnet.ibm.com, benh@kernel.crashing.org David Gibson writes: > [ Unknown signature status ] > On Tue, Jul 12, 2016 at 11:33:17PM +0530, Nikunj A Dadhania wrote: >> From: "Aneesh Kumar K.V" >> >> Signed-off-by: Aneesh Kumar K.V >> [ rebased and added POWER9 alias ] >> Signed-off-by: Nikunj A Dadhania >> --- >> target-ppc/cpu-models.c | 5 +++ >> target-ppc/cpu-models.h | 2 ++ >> target-ppc/cpu-qom.h | 7 ++++ >> target-ppc/mmu_helper.c | 3 +- >> target-ppc/translate_init.c | 85 ++++++++++++++++++++++++++++++++++++++++++++- >> 5 files changed, 100 insertions(+), 2 deletions(-) >> >> diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c >> index 5209e63..901cf40 100644 >> --- a/target-ppc/cpu-models.c >> +++ b/target-ppc/cpu-models.c >> @@ -1147,6 +1147,10 @@ >> "POWER8NVL v1.0") >> POWERPC_DEF("970_v2.2", CPU_POWERPC_970_v22, 970, >> "PowerPC 970 v2.2") >> + >> + POWERPC_DEF("POWER9_v1.0", CPU_POWERPC_POWER9_BASE, POWER9, >> + "POWER9 v1.0") >> + >> POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970, >> "PowerPC 970FX v1.0 (G5)") >> POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970, >> @@ -1395,6 +1399,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = { >> { "POWER8E", "POWER8E_v2.1" }, >> { "POWER8", "POWER8_v2.0" }, >> { "POWER8NVL", "POWER8NVL_v1.0" }, >> + { "POWER9", "POWER9_v1.0" }, >> { "970", "970_v2.2" }, >> { "970fx", "970fx_v3.1" }, >> { "970mp", "970mp_v1.1" }, >> diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h >> index f21a44c..beeaaba 100644 >> --- a/target-ppc/cpu-models.h >> +++ b/target-ppc/cpu-models.h >> @@ -562,6 +562,8 @@ enum { >> CPU_POWERPC_POWER8_v20 = 0x004D0200, >> CPU_POWERPC_POWER8NVL_BASE = 0x004C0000, >> CPU_POWERPC_POWER8NVL_v10 = 0x004C0100, >> + CPU_POWERPC_POWER9_BASE = 0x004E0000, >> + CPU_POWERPC_POWER9_MAM = 0x004E0100, >> CPU_POWERPC_970_v22 = 0x00390202, >> CPU_POWERPC_970FX_v10 = 0x00391100, >> CPU_POWERPC_970FX_v20 = 0x003C0200, >> diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h >> index 2864105..df2fb65 100644 >> --- a/target-ppc/cpu-qom.h >> +++ b/target-ppc/cpu-qom.h >> @@ -86,6 +86,13 @@ enum powerpc_mmu_t { >> POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG >> | POWERPC_MMU_64K >> | POWERPC_MMU_AMR | 0x00000004, >> + /* for now , We can add radix later if needed */ > > I'm guessing this means you're only thinking about the guest-side > presentation of the P9 MMU at this point? IIUC the host side > presentation is so different that sharing any constants with pre-P9 > MMUs probably doesn't make sense. > > I'm not immediately sure how we should make this distinction in the > target-ppc code, since these values are supposed to belong to the CPU > regardless of operating mode. Currently, this is just a place holder patch. Not close to committing yet. For me to add the new instruction needed these family defines. Regards, Nikunj