From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0ECD7C433EF for ; Sat, 18 Jun 2022 10:39:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232373AbiFRKjP (ORCPT ); Sat, 18 Jun 2022 06:39:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229721AbiFRKjN (ORCPT ); Sat, 18 Jun 2022 06:39:13 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8576518E1A for ; Sat, 18 Jun 2022 03:39:12 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E1A3860EEC for ; Sat, 18 Jun 2022 10:39:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1FE04C3411A; Sat, 18 Jun 2022 10:39:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655548751; bh=mFqR2zYUPtwxPjuUXQybAP/brbw1NZVrYlFLtMYaj+I=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=OKeSkkupAGsG1uFEOvzXEpaYGjoABzWLBuYYUWNavpoX2QFoK6X2jI8/+wahuKfZo hgVCUpYZ5y2wEi8uWMVPdbYocOahkv2HqZYgfSUatXirK/A1uyWCE5VpLWGfsswl3X WmwaDDFlkwDhtpd8pgITp+X7QevM/SMGqmfXX4/yCDB3JLdvfJxT5yhKQ4m7Qhb+eD 5VY0D4zDoTKwos9+xqZw8evVvTSa52eLaMwnXNLaLqXMiMS0afvo6SJdZ7pDfDG/+M uPyCsHRUfbMVc+Y/HsvHH8oCIWKy/fs/eGvLJX7gQmOFqvY0dkyruAtMamBX6ZbhjW NSpzRMtwXl9+g== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1o2VrA-001Sqc-Mb; Sat, 18 Jun 2022 11:39:08 +0100 Date: Sat, 18 Jun 2022 11:39:09 +0100 Message-ID: <87edzmp86q.wl-maz@kernel.org> From: Marc Zyngier To: Jianmin Lv Cc: Thomas Gleixner , linux-kernel@vger.kernel.org, Hanjun Guo , Lorenzo Pieralisi , Jiaxun Yang , Huacai Chen Subject: Re: [PATCH V12 00/10] irqchip: Add LoongArch-related irqchip drivers In-Reply-To: <1655273250-23495-1-git-send-email-lvjianmin@loongson.cn> References: <1655273250-23495-1-git-send-email-lvjianmin@loongson.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lvjianmin@loongson.cn, tglx@linutronix.de, linux-kernel@vger.kernel.org, guohanjun@huawei.com, lorenzo.pieralisi@arm.com, jiaxun.yang@flygoat.com, chenhuacai@loongson.cn X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 15 Jun 2022 07:07:20 +0100, Jianmin Lv wrote: >=20 > LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. > LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit > version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its > boot protocol LoongArch-specific interrupt controllers (similar to APIC) > are already added in the ACPI Specification 6.5(which may be published in > early June this year and the board is reviewing the draft). >=20 > Currently, LoongArch based processors (e.g. Loongson-3A5000) can only > work together with LS7A chipsets. The irq chips in LoongArch computers > include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O > Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller), > HTVECINTC (Hyper-Transport Vector Interrupt Controller), PCH-PIC (Main > Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller > in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). >=20 > CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are > per-package controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are all > controllers out of CPU (i.e., in chipsets). These controllers (in other > words, irqchips) are linked in a hierarchy, and there are two models of > hierarchy (legacy model and extended model).=20 >=20 > Legacy IRQ model: >=20 > In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer > interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, > while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and > gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC. >=20 > +---------------------------------------------+ > | | > | +-----+ +---------+ +-------+ | > | | IPI | --> | CPUINTC | <-- | Timer | | > | +-----+ +---------+ +-------+ | > | ^ | > | | | > | +---------+ +-------+ | > | | LIOINTC | <-- | UARTs | | > | +---------+ +-------+ | > | ^ | > | | | > | +-----------+ | > | | HTVECINTC | | > | +-----------+ | > | ^ ^ | > | | | | > | +---------+ +---------+ | > | | PCH-PIC | | PCH-MSI | | > | +---------+ +---------+ | > | ^ ^ ^ | > | | | | | > | +---------+ +---------+ +---------+ | > | | PCH-LPC | | Devices | | Devices | | > | +---------+ +---------+ +---------+ | > | ^ | > | | | > | +---------+ | > | | Devices | | > | +---------+ | > | | > | | > +---------------------------------------------+ >=20 > Extended IRQ model: >=20 > In this model, the IPI (Inter-Processor Interrupt) and CPU Local Timer > interrupt go to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, > while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and > gathered by EIOINTC, and then go to to CPUINTC directly. >=20 > +--------------------------------------------------------+ > | | > | +-----+ +---------+ +-------+ | > | | IPI | --> | CPUINTC | <-- | Timer | | > | +-----+ +---------+ +-------+ | > | ^ ^ | > | | | | > | +---------+ +---------+ +-------+ | > | | EIOINTC | | LIOINTC | <-- | UARTs | | > | +---------+ +---------+ +-------+ | > | ^ ^ | > | | | | > | +---------+ +---------+ | > | | PCH-PIC | | PCH-MSI | | > | +---------+ +---------+ | > | ^ ^ ^ | > | | | | | > | +---------+ +---------+ +---------+ | > | | PCH-LPC | | Devices | | Devices | | > | +---------+ +---------+ +---------+ | > | ^ | > | | | > | +---------+ | > | | Devices | | > | +---------+ | > | | > | | > +--------------------------------------------------------+ >=20 > The hierarchy model is constructed by parsing irq contronler structures > in MADT. Some controllers((e.g. LIOINTC, HTVECINTC, EIOINTC and PCH-LPC) > are hardcodingly connected to their parents, so their irqdomins are > separately routed to their parents in a fixed way. Some controllers > (e.g. PCH-PIC and PCH-MSI) could be routed to different parents for diffe= rent > CPU. The firmware will config EIOINTC for the newer CPU and config HTVECI= NTC > for old CPU in MADT. By this way, PCH-PIC and PCH-MSI irqdomain can only = be > routed one parent irqdomin: HTVECINTC or EIOINTC. >=20 >=20 > Example of irqchip topology in a system with two chipsets: >=20 > +------------------------------------------------------------+ > | | > | +------------------+ | > | | CPUINTC | | > | +------------------+ | > | ^ ^ | > | | | | > | +----------+ +----------+ | > | | EIOINTC 0| | EIOINTC 1| | > | +----------+ +----------+ | > | ^ ^ ^ ^ | > | | | | | | > | +----------+ +----------+ +----------+ +----------+ | > | | PCH-PIC 0| | PCH-MSI 0| | PCH-PIC 1| | PCH-MSI 1| | > | +----------+ +----------+ +----------+ +----------+ | > | | > | | > +------------------------------------------------------------+ >=20 > For systems with two chipsets, there are tow group(consists of EIOINTC, P= CH-PIC and PCH-MSI) irqdomains,=20 > and each group has same node id. So we defined a structure to mantain the= relation of node and it's parent irqdomain. >=20 > struct acpi_vector_group { > int node; > struct irq_domain *parent; > }; >=20 > The initialization and use of acpi_vector_group array are following: >=20 > 1 Entry of struct acpi_vector_group array initialization: >=20 > By parsing MCFG, the node id=EF=BC=88from bit44-47 of Base Address=EF=BC= =89of each pci segment is extracted. And from MADT, we have the node id of = each EIOINTC. >=20 > entrys[pci segment].node =3D node id of pci segment > entrys[pci segment].parent =3D EIOINTC irqdomain(node id of EIOINTC =3D= =3D node id of pci segment) >=20 > 2 Get parent irqdomain for PCH-PIC: >=20 > From MADT, we have the node id of each PCH-PIC(from bit44-47 of Base Addr= ess). > if (node of entry i =3D=3D node of PCH-PIC) > return entrys[i].parent; >=20 > entrys[pci segment].node =3D node id of pci segment > entrys[pci segment].parent =3D EIOINTC irqdomain(node id of EIOINTC =3D= =3D node id of pci segment) >=20 > 3 Get parent irqdomain for PCH-MSI of pci segment: >=20 > return entrys[pci segment].parent; >=20 > 4 How to select a correct irqdomain to map irq for a device? > For devices using legacy irq behind PCH-PIC, GSI is used to select correc= t PCH-PIC irqdomain. > For devices using msi irq behind PCH-MSI, the pci segmen of the device is= used to select correct PCH-MSI irqdomain. >=20 > V1 -> V2: > 1, Remove queued patches; > 2, Move common logic of DT/ACPI probing to common functions; > 3, Split .suspend()/.resume() functions to separate patches. >=20 > V2 -> V3: > 1, Fix a bug for loongson-pch-pic probe; > 2, Some minor improvements for LPC controller. >=20 > V3 -> V4: > 1, Rework the CPU interrupt controller driver; > 2, Some minor improvements for other controllers. >=20 > V4 -> V5: > 1, Add a description of LoonArch's IRQ model; > 2, Support multiple EIOINTCs in one system; > 3, Some minor improvements for other controllers. >=20 > V5 -> V6: > 1, Attach a fwnode to CPUINTC irq domain; > 2, Use raw spinlock instead of generic spinlock; > 3, Improve the method of restoring EIOINTC state; > 4, Update documentation, comments and commit messages. >=20 > V6 -> V7: > 1, Fix build warnings reported by kernel test robot. >=20 > V7 -> V8: > 1, Add arguments sanity checking for irqchip init functions; > 2, Support Loongson-3C5000 (One NUMA Node includes 4 EIOINTC Node). >=20 > V8 -> V9: > 1, Rebase on 5.17-rc5; > 2, Update cover letter; > 3, Some small improvements. >=20 > V9 -> V10: > 1, Rebase on 5.17-rc6; > 2, Fix build warnings reported by kernel test robot. >=20 > V10 -> V11: > 1, Rebase on 5.18-rc4; > 2, Fix irq affinity setting for EIOINTC; > 3, Fix hwirq allocation failure for EIOINTC. >=20 > V11 -> RFC: > 1, Refactored the way to build irqchip hierarchy topology. >=20 > RFC -> RFC V2: > 1, Move all IO-interrupt related code to driver/irqchip from arch directo= ry. > 2. Add description for an example of two chipsets system. >=20 > RFC V2 -> RFC V3: > 1, Add support for multiple GSI domains > 2, Use ACPI_GENERIC_GSI for GSI handling > 3, Drop suspend-resume stuff > 4, Export fwnode handles instead of irq domain handles >=20 > RFC V3 -> V12: > 1, Address patch attributions of the patch series >=20 > Huacai Chen (7): > irqchip: Add LoongArch CPU interrupt controller support > irqchip/loongson-pch-pic: Add ACPI init support > irqchip/loongson-pch-msi: Add ACPI init support > irqchip/loongson-htvec: Add ACPI init support > irqchip/loongson-liointc: Add ACPI init support > irqchip: Add Loongson Extended I/O interrupt controller support > irqchip: Add Loongson PCH LPC controller support >=20 > Jianmin Lv (2): > genirq/generic_chip: export irq_unmap_generic_chip > irqchip: create library file for LoongArch irqchip driver >=20 > Marc Zyngier (1): > APCI: irq: Add support for multiple GSI domains >=20 > drivers/acpi/bus.c | 3 + > drivers/acpi/irq.c | 40 ++-- > drivers/irqchip/Kconfig | 28 +++ > drivers/irqchip/Makefile | 3 + > drivers/irqchip/irq-gic-v3.c | 18 +- > drivers/irqchip/irq-gic.c | 18 +- > drivers/irqchip/irq-loongarch-cpu.c | 134 +++++++++++ > drivers/irqchip/irq-loongarch-pic-common.c | 122 ++++++++++ > drivers/irqchip/irq-loongarch-pic-common.h | 39 ++++ > drivers/irqchip/irq-loongson-eiointc.c | 347 +++++++++++++++++++++++= ++++++ > drivers/irqchip/irq-loongson-htvec.c | 119 +++++++--- > drivers/irqchip/irq-loongson-liointc.c | 225 ++++++++++++------- > drivers/irqchip/irq-loongson-pch-lpc.c | 202 +++++++++++++++++ > drivers/irqchip/irq-loongson-pch-msi.c | 138 ++++++++---- > drivers/irqchip/irq-loongson-pch-pic.c | 171 +++++++++++--- > include/linux/acpi.h | 3 +- > include/linux/cpuhotplug.h | 1 + > include/linux/irq.h | 1 + > kernel/irq/generic-chip.c | 2 +- > 19 files changed, 1402 insertions(+), 212 deletions(-) > create mode 100644 drivers/irqchip/irq-loongarch-cpu.c > create mode 100644 drivers/irqchip/irq-loongarch-pic-common.c > create mode 100644 drivers/irqchip/irq-loongarch-pic-common.h > create mode 100644 drivers/irqchip/irq-loongson-eiointc.c > create mode 100644 drivers/irqchip/irq-loongson-pch-lpc.c One thing I don't see here is the removal of the irq code that currently lives in arch/loongarch/kernel/acpi.c. It really should be removed as part of this series with the patch that enables the common ACPI irq code for this architecture. Thanks, M. --=20 Without deviation from the norm, progress is not possible.