From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C49F7C433E0 for ; Tue, 23 Jun 2020 06:09:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ABF6A20656 for ; Tue, 23 Jun 2020 06:09:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730370AbgFWGJ0 (ORCPT ); Tue, 23 Jun 2020 02:09:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728800AbgFWGJ0 (ORCPT ); Tue, 23 Jun 2020 02:09:26 -0400 Received: from Galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62F97C061573; Mon, 22 Jun 2020 23:09:26 -0700 (PDT) Received: from p5b06d650.dip0.t-ipconnect.de ([91.6.214.80] helo=kurt) by Galois.linutronix.de with esmtpsa (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1jnc7Y-0001vL-Gb; Tue, 23 Jun 2020 08:09:24 +0200 From: Kurt Kanzenbach To: Andrew Lunn Cc: Vivien Didelot , Florian Fainelli , "David S. Miller" , Jakub Kicinski , netdev@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org, Sebastian Andrzej Siewior , Richard Cochran , Kamil Alkhouri , ilias.apalodimas@linaro.org Subject: Re: [RFC PATCH 9/9] dt-bindings: net: dsa: Add documentation for Hellcreek switches In-Reply-To: <20200622134946.GM338481@lunn.ch> References: <20200618064029.32168-1-kurt@linutronix.de> <20200618064029.32168-10-kurt@linutronix.de> <20200618134704.GQ249144@lunn.ch> <87zh8zphlc.fsf@kurt> <20200619135657.GF304147@lunn.ch> <87imfjtik4.fsf@kurt> <20200622134946.GM338481@lunn.ch> Date: Tue, 23 Jun 2020 08:09:18 +0200 Message-ID: <87eeq6nwj5.fsf@kurt> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha512; protocol="application/pgp-signature" X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable On Mon Jun 22 2020, Andrew Lunn wrote: > On Mon, Jun 22, 2020 at 02:02:19PM +0200, Kurt Kanzenbach wrote: >> On Fri Jun 19 2020, Andrew Lunn wrote: >> >> > The switch is 100/100Mbps right? The MAC is only Fast ethernet. Do = you >> >> > need some properties in the port@0 node to tell the switch to only = use >> >> > 100Mbps? I would expect it to default to 1G. Not looked at the code >> >> > yet... >> >>=20 >> >> No, that is not needed. That is a hardware configuration and AFAIK >> >> cannot be changed at run time. >> > >> > I was wondering about that in general. I did not spot any code in the >> > driver dealing with results from the PHY auto-neg. So you are saying >> > the CPU is fixed speed, by strapping? But what about the other ports? >> > Does the MAC need to know the PHY has negotiated 10Half, not 1G? Would >> > that not make a difference to your TSN? >>=20 >> Indeed, that does make a difference. I've checked with the vendor. The >> current version of the switch IP does not support configuring the speed >> etc. at run time. It is hard wired to 100 Mbit/s or 1000 Mbit/s for >> now. Later versions of the chip might support setting the speed etc. via >> configuration registers. As a result the PHYs at the front ports should >> be programmed to only advertise 100 Mbit/s or 1G depending on the >> hardware setup. > > Hi Kurt > > Are there registers which allow you to determine the strapping? No, there are not. > There are phylib/phylink calls you can make to set the advertisement > in the PHY. It would be good to do this in the DSA driver. I will. All the chips currently available are configured to 100 Mbit/s. So, we can assume that for now. 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