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Date: Wed, 04 Aug 2021 16:44:20 -0700
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From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
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Subject: Re: [igt-dev] [PATCH i-g-t v3 06/52] lib/intel_batchbuffer: Add
 allocator support in blitter src copy
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To: Zbigniew =?ISO-8859-2?Q?Kempczy=F1ski?= <zbigniew.kempczynski@intel.com>
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On Wed, 04 Aug 2021 16:26:32 -0700, Dixit, Ashutosh wrote:
>
> On Mon, 26 Jul 2021 12:59:40 -0700, Zbigniew Kempczy=F1ski wrote:
> >
> > @@ -808,9 +816,21 @@ void igt_blitter_src_copy(int fd,
> >	uint32_t src_pitch, dst_pitch;
> >	uint32_t dst_reloc_offset, src_reloc_offset;
> >	uint32_t gen =3D intel_gen(intel_get_drm_devid(fd));
> > +	uint64_t batch_offset, src_offset, dst_offset;
> >	const bool has_64b_reloc =3D gen >=3D 8;
> >	int i =3D 0;
> >
> > +	batch_handle =3D gem_create(fd, 4096);
> > +	if (ahnd) {
> > +		src_offset =3D get_offset(ahnd, src_handle, src_size, 0);
> > +		dst_offset =3D get_offset(ahnd, dst_handle, dst_size, 0);
> > +		batch_offset =3D get_offset(ahnd, batch_handle, 4096, 0);
> > +	} else {
> > +		src_offset =3D 16 << 20;
> > +		dst_offset =3D ALIGN(src_offset + src_size, 1 << 20);
> > +		batch_offset =3D ALIGN(dst_offset + dst_size, 1 << 20);
>
> For the !ahnd case, we are providing relocations right? We still need to
> provide these offsets or they can all be 0?

This is probably needed because of I915_EXEC_NO_RELOC added in the next
patch (Patch 07/20)?