From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gregory CLEMENT Subject: Re: [PATCH 2/2] arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal Date: Fri, 30 Nov 2018 18:45:35 +0100 Message-ID: <87ftvimpc0.fsf@bootlin.com> References: Mime-Version: 1.0 Content-Type: text/plain Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , linux-arm-kernel@lists.infradead.org, Russell King , Ori Shemtov , Florian Fainelli , netdev@vger.kernel.org, Linus Walleij To: Baruch Siach Return-path: Received: from mail.bootlin.com ([62.4.15.54]:33705 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726881AbeLAEzi (ORCPT ); Fri, 30 Nov 2018 23:55:38 -0500 In-Reply-To: (Baruch Siach's message of "Tue, 16 Oct 2018 13:50:53 +0300") Sender: netdev-owner@vger.kernel.org List-ID: Hi Baruch, On mar., oct. 16 2018, Baruch Siach wrote: > This reset signal controls the Marvell 1512 1G PHY. > > Note that current implementation queries the PHY over the MDIO bus > (get_phy_device() call from of_mdiobus_register_phy()) before reset > signal deassert. If the PHY reset signal is asserted at boot time, PHY > registration fails. So current code relies on the bootloader to deassert > the reset signal. Applied on mvebu/dt64 Thanks, Gregory > > Signed-off-by: Baruch Siach > --- > arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts > index af1310c53bc8..73df0ef5e0c4 100644 > --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts > +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts > @@ -337,6 +337,10 @@ > */ > marvell,reg-init = <3 16 0 0x1017>; > reg = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&cp0_copper_eth_phy_reset>; > + reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; > + reset-assert-us = <10000>; > }; > > switch0: switch0@4 { > -- > 2.19.1 > -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF5FEC04EB8 for ; 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Fri, 30 Nov 2018 18:45:35 +0100 (CET) From: Gregory CLEMENT To: Baruch Siach Subject: Re: [PATCH 2/2] arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal References: Date: Fri, 30 Nov 2018 18:45:35 +0100 In-Reply-To: (Baruch Siach's message of "Tue, 16 Oct 2018 13:50:53 +0300") Message-ID: <87ftvimpc0.fsf@bootlin.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181130_094546_885087_E2816FFB X-CRM114-Status: GOOD ( 16.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Florian Fainelli , Jason Cooper , netdev@vger.kernel.org, Linus Walleij , Russell King , Ori Shemtov , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Baruch, On mar., oct. 16 2018, Baruch Siach wrote: > This reset signal controls the Marvell 1512 1G PHY. > > Note that current implementation queries the PHY over the MDIO bus > (get_phy_device() call from of_mdiobus_register_phy()) before reset > signal deassert. If the PHY reset signal is asserted at boot time, PHY > registration fails. So current code relies on the bootloader to deassert > the reset signal. Applied on mvebu/dt64 Thanks, Gregory > > Signed-off-by: Baruch Siach > --- > arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts > index af1310c53bc8..73df0ef5e0c4 100644 > --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts > +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts > @@ -337,6 +337,10 @@ > */ > marvell,reg-init = <3 16 0 0x1017>; > reg = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&cp0_copper_eth_phy_reset>; > + reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; > + reset-assert-us = <10000>; > }; > > switch0: switch0@4 { > -- > 2.19.1 > -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel