From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60684) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkTA1-0006Wg-Oh for qemu-devel@nongnu.org; Thu, 15 Sep 2016 05:40:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bkT9x-0005Kn-9j for qemu-devel@nongnu.org; Thu, 15 Sep 2016 05:40:48 -0400 Received: from mail-wm0-f53.google.com ([74.125.82.53]:38669) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkT9w-0005KO-RB for qemu-devel@nongnu.org; Thu, 15 Sep 2016 05:40:45 -0400 Received: by mail-wm0-f53.google.com with SMTP id 1so81369898wmz.1 for ; Thu, 15 Sep 2016 02:40:44 -0700 (PDT) References: <1472935202-3342-1-git-send-email-rth@twiddle.net> <1472935202-3342-33-git-send-email-rth@twiddle.net> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1472935202-3342-33-git-send-email-rth@twiddle.net> Date: Thu, 15 Sep 2016 10:39:42 +0100 Message-ID: <87fup1ijs1.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v3 32/34] target-arm: remove EXCP_STREX + cpu_exclusive_{test, info} List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, "Emilio G. Cota" Richard Henderson writes: > From: "Emilio G. Cota" > > The exception is not emitted anymore; remove it and the associated > TCG variables. > > Signed-off-by: Emilio G. Cota > Signed-off-by: Richard Henderson > Message-Id: <1467054136-10430-31-git-send-email-cota@braap.org> > --- > target-arm/cpu.h | 17 ++++++----------- > target-arm/internals.h | 4 +--- > target-arm/translate.c | 10 ---------- > target-arm/translate.h | 4 ---- > 4 files changed, 7 insertions(+), 28 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 76d824d..a38cec0 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -46,13 +46,12 @@ > #define EXCP_BKPT 7 > #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ > #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ > -#define EXCP_STREX 10 > -#define EXCP_HVC 11 /* HyperVisor Call */ > -#define EXCP_HYP_TRAP 12 > -#define EXCP_SMC 13 /* Secure Monitor Call */ > -#define EXCP_VIRQ 14 > -#define EXCP_VFIQ 15 > -#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */ > +#define EXCP_HVC 10 /* HyperVisor Call */ > +#define EXCP_HYP_TRAP 11 > +#define EXCP_SMC 12 /* Secure Monitor Call */ > +#define EXCP_VIRQ 13 > +#define EXCP_VFIQ 14 > +#define EXCP_SEMIHOST 15 /* semihosting call (A64 only) */ > > #define ARMV7M_EXCP_RESET 1 > #define ARMV7M_EXCP_NMI 2 > @@ -475,10 +474,6 @@ typedef struct CPUARMState { > uint64_t exclusive_addr; > uint64_t exclusive_val; > uint64_t exclusive_high; > -#if defined(CONFIG_USER_ONLY) > - uint64_t exclusive_test; > - uint32_t exclusive_info; > -#endif > > /* iwMMXt coprocessor state. */ > struct { > diff --git a/target-arm/internals.h b/target-arm/internals.h > index cd57401..3edccd2 100644 > --- a/target-arm/internals.h > +++ b/target-arm/internals.h > @@ -46,8 +46,7 @@ static inline bool excp_is_internal(int excp) > || excp == EXCP_HALTED > || excp == EXCP_EXCEPTION_EXIT > || excp == EXCP_KERNEL_TRAP > - || excp == EXCP_SEMIHOST > - || excp == EXCP_STREX; > + || excp == EXCP_SEMIHOST; > } > > /* Exception names for debug logging; note that not all of these > @@ -63,7 +62,6 @@ static const char * const excnames[] = { > [EXCP_BKPT] = "Breakpoint", > [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", > [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", > - [EXCP_STREX] = "QEMU intercept of STREX", > [EXCP_HVC] = "Hypervisor Call", > [EXCP_HYP_TRAP] = "Hypervisor Trap", > [EXCP_SMC] = "Secure Monitor Call", > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 2b3c34f..e8e8502 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -64,10 +64,6 @@ static TCGv_i32 cpu_R[16]; > TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; > TCGv_i64 cpu_exclusive_addr; > TCGv_i64 cpu_exclusive_val; > -#ifdef CONFIG_USER_ONLY > -TCGv_i64 cpu_exclusive_test; > -TCGv_i32 cpu_exclusive_info; > -#endif > > /* FIXME: These should be removed. */ > static TCGv_i32 cpu_F0s, cpu_F1s; > @@ -101,12 +97,6 @@ void arm_translate_init(void) > offsetof(CPUARMState, exclusive_addr), "exclusive_addr"); > cpu_exclusive_val = tcg_global_mem_new_i64(cpu_env, > offsetof(CPUARMState, exclusive_val), "exclusive_val"); > -#ifdef CONFIG_USER_ONLY > - cpu_exclusive_test = tcg_global_mem_new_i64(cpu_env, > - offsetof(CPUARMState, exclusive_test), "exclusive_test"); > - cpu_exclusive_info = tcg_global_mem_new_i32(cpu_env, > - offsetof(CPUARMState, exclusive_info), "exclusive_info"); > -#endif > > a64_translate_init(); > } > diff --git a/target-arm/translate.h b/target-arm/translate.h > index dbd7ac8..d4e205e 100644 > --- a/target-arm/translate.h > +++ b/target-arm/translate.h > @@ -77,10 +77,6 @@ extern TCGv_env cpu_env; > extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; > extern TCGv_i64 cpu_exclusive_addr; > extern TCGv_i64 cpu_exclusive_val; > -#ifdef CONFIG_USER_ONLY > -extern TCGv_i64 cpu_exclusive_test; > -extern TCGv_i32 cpu_exclusive_info; > -#endif > > static inline int arm_dc_feature(DisasContext *dc, int feature) > { Reviewed-by: Alex Bennée -- Alex Bennée