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From: Fabiano Rosas <farosas@linux.ibm.com>
To: "Cédric Le Goater" <clg@kaod.org>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com,
	richard.henderson@linaro.org, david@gibson.dropbear.id.au
Subject: Re: [PATCH] target/ppc: powerpc_excp: Guard ALIGNMENT interrupt with CONFIG_TCG
Date: Thu, 09 Dec 2021 14:26:17 -0300	[thread overview]
Message-ID: <87h7bh666e.fsf@linux.ibm.com> (raw)
In-Reply-To: <a2cca719-7d28-65a1-97c4-c91d9a469cbf@kaod.org>

Cédric Le Goater <clg@kaod.org> writes:

> Richard,
>
> On 12/9/21 16:05, Fabiano Rosas wrote:
>> Cédric Le Goater <clg@kaod.org> writes:
>> 
>>> On 12/9/21 00:06, Fabiano Rosas wrote:
>>>> We cannot have TCG code in powerpc_excp because the function is called
>>>> from kvm-only code via ppc_cpu_do_interrupt:
>>>>
>>>>    ../target/ppc/excp_helper.c:463:29: error: implicit declaration of
>>>>    function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration]
>>>>
>>>> Fortunately, the Alignment interrupt is not among the ones dispatched
>>>> from kvm-only code, so we can keep it out of the disable-tcg build for
>>>> now.
>>>>
>>>> Fixes: 336e91f853 ("target/ppc: Move SPR_DSISR setting to powerpc_excp")
>>>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>>>>
>>>> ---
>>>>
>>>> Perhaps we could make powerpc_excp TCG only and have a separate
>>>> function that only knows the two interrupts that we use with KVM
>>>> (Program, Machine check). But for now this fix will do, I think.
>>>> ---
>>>>    target/ppc/excp_helper.c | 2 ++
>>>>    1 file changed, 2 insertions(+)
>>>>
>>>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>>>> index 17607adbe4..dcf22440cc 100644
>>>> --- a/target/ppc/excp_helper.c
>>>> +++ b/target/ppc/excp_helper.c
>>>> @@ -453,6 +453,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
>>>>            }
>>>>            break;
>>>>        }
>>>> +#ifdef CONFIG_TCG
>>>>        case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
>>>>            /*
>>>>             * Get rS/rD and rA from faulting opcode.
>>>> @@ -464,6 +465,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
>>>>                env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16;
>>>>            }
>>>>            break;
>>>> +#endif
>>>>        case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
>>>>            switch (env->error_code & ~0xF) {
>>>>            case POWERPC_EXCP_FP:
>>>>
>>>
>>> Shouldn't we move that code under ppc_cpu_do_unaligned_access ?
>> 
>> Well, it came from there initially. We could revert 336e91f853 and that
>> would fix the issue as well.
>
> What would you prefer ?

Well none of this interfere with the work I'm doing, so it really makes
no difference. I guess reverting the patch is cleaner than having an
ifdef loose in the middle of the code. I'll send a v2 with the revert.

>
> Thanks,
>
> C.


  reply	other threads:[~2021-12-09 17:28 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-08 23:06 [PATCH] target/ppc: powerpc_excp: Guard ALIGNMENT interrupt with CONFIG_TCG Fabiano Rosas
2021-12-09  9:14 ` Philippe Mathieu-Daudé
2021-12-09 15:22   ` Fabiano Rosas
2021-12-09 14:38 ` Cédric Le Goater
2021-12-09 15:05   ` Fabiano Rosas
2021-12-09 15:18     ` Cédric Le Goater
2021-12-09 17:26       ` Fabiano Rosas [this message]
2021-12-09 19:15         ` Fabiano Rosas

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