From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66F60C43464 for ; Fri, 18 Sep 2020 10:22:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D9D1208C3 for ; Fri, 18 Sep 2020 10:22:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600424525; bh=Uu+bmGTBgLjg7wVQ/owRSKt7ej5xLC0BHxLGBSXNJFk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=qnoKI02Vd1ovGr8N4/iGeFJsFZekLpjsFvMRwlEVPLKPLVCD2vInpzglTlDDR/ea4 tAiHf72SWNeaPLvb9PQ4NIJCoz12rVm3//uX/70FrZnVhYPd/rkpvuviy07M7TBw/l mVddMqdEw/9CMKkmGu8w9A80GC8UgTrNMIxyH3nY= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726427AbgIRKWE (ORCPT ); Fri, 18 Sep 2020 06:22:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:58110 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726304AbgIRKWD (ORCPT ); Fri, 18 Sep 2020 06:22:03 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id DC3AD208DB; Fri, 18 Sep 2020 10:22:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600424523; bh=Uu+bmGTBgLjg7wVQ/owRSKt7ej5xLC0BHxLGBSXNJFk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=HAKa1fFCgkk1s9z9BmartTRBp+oRtYqvpG2VuZDxgJlHF/XXDfCRqqX1wpxO5yHFE QvUvIETGi5Oy0/Al4sDSdP8Adq/A3qIDLQNhiIgRn7Lub+i5RxveP5yDGRXdabPUiW GWC1l5ha0cb3+SaBgg+qbjTbbawS9/cXoKVK/uCo= Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kJDWj-00CxiS-0u; Fri, 18 Sep 2020 11:22:01 +0100 Date: Fri, 18 Sep 2020 11:21:59 +0100 Message-ID: <87h7rvqta0.wl-maz@kernel.org> From: Marc Zyngier To: James Morse Cc: jonathanh@nvidia.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sumit Garg , kernel-team@android.com, Florian Fainelli , Russell King , Jason Cooper , Saravana Kannan , Andrew Lunn , Catalin Marinas , Gregory Clement , Thomas Gleixner , Will Deacon , Valentin Schneider Subject: Re: [PATCH v3 08/16] irqchip/gic: Configure SGIs as standard interrupts In-Reply-To: References: <20200901144324.1071694-1-maz@kernel.org> <20200901144324.1071694-9-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26.3 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: james.morse@arm.com, jonathanh@nvidia.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sumit.garg@linaro.org, kernel-team@android.com, f.fainelli@gmail.com, linux@arm.linux.org.uk, jason@lakedaemon.net, saravanak@google.com, andrew@lunn.ch, catalin.marinas@arm.com, gregory.clement@bootlin.com, tglx@linutronix.de, will@kernel.org, valentin.schneider@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi James, On Fri, 18 Sep 2020 10:58:45 +0100, James Morse wrote: > > Hi Marc, > > (CC: +Jon) > > On 01/09/2020 15:43, Marc Zyngier wrote: > > Change the way we deal with GIC SGIs by turning them into proper > > IRQs, and calling into the arch code to register the interrupt range > > instead of a callback. > > Your comment "This only works because we don't nest SGIs..." on this > thread tripped some bad memories from adding the irq-stack. Softirq > causes us to nest irqs, but only once. > > > (I've messed with the below diff to remove the added stuff:) > > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > > index 4ffd62af888f..4be2b62f816f 100644 > > --- a/drivers/irqchip/irq-gic.c > > +++ b/drivers/irqchip/irq-gic.c > > @@ -335,31 +335,22 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) > > irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); > > irqnr = irqstat & GICC_IAR_INT_ID_MASK; > > > > - if (likely(irqnr > 15 && irqnr < 1020)) { > > - if (static_branch_likely(&supports_deactivate_key)) > > - writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); > > - isb(); > > - handle_domain_irq(gic->domain, irqnr, regs); > > - continue; > > - } > > - if (irqnr < 16) { > > writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); > > - if (static_branch_likely(&supports_deactivate_key)) > > - writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); > > -#ifdef CONFIG_SMP > > - /* > > - * Ensure any shared data written by the CPU sending > > - * the IPI is read after we've read the ACK register > > - * on the GIC. > > - * > > - * Pairs with the write barrier in gic_raise_softirq > > - */ > > smp_rmb(); > > - handle_IPI(irqnr, regs); > > If I read this right, previously we would EOI the interrupt before > calling handle_IPI(). Where as now with the version of this series > in your tree, we stuff the to-be-EOId value in a percpu variable, > which is only safe if these don't nest. > > Hidden in irq_exit(), kernel/softirq.c::__irq_exit_rcu() has this: > | preempt_count_sub(HARDIRQ_OFFSET); > | if (!in_interrupt() && local_softirq_pending()) > | invoke_softirq(); > > The arch code doesn't raise the preempt counter by HARDIRQ, so once > __irq_exit_rcu() has dropped it, in_interrupt() returns false, and > we invoke_softirq(). > > invoke_softirq() -> __do_softirq() -> local_irq_enable()! > > Fortunately, __do_softirq() raises the softirq count first using > __local_bh_disable_ip(), which in-interrupt() checks too, so this > can only happen once per IRQ. > > Now the irq_exit() has moved from handle_IPI(), which ran after EOI, > into handle_domain_irq(), which runs before. I think its possible > SGIs nest, and the new percpu variable becomes corrupted. I can't see how. The interrupt is active until we EOI/deactivate it, and thus cannot be observed again by the CPU interface until this happens. Furthermore, irq_exit() in __handle_domain_irq() is *after* the EOI anyway (generic_handle_irq_() directly calls the flow, which immediately EOIs the interrupt). The only material change is that irq_enter() happens before EOI. Is that what you are referring to? Thanks, M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCA0DC43463 for ; Fri, 18 Sep 2020 10:25:20 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 81910208C3 for ; Fri, 18 Sep 2020 10:25:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="HJP0/2c4"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="HAKa1fFC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 81910208C3 Authentication-Results: mail.kernel.org; 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Fri, 18 Sep 2020 11:22:01 +0100 Date: Fri, 18 Sep 2020 11:21:59 +0100 Message-ID: <87h7rvqta0.wl-maz@kernel.org> From: Marc Zyngier To: James Morse Subject: Re: [PATCH v3 08/16] irqchip/gic: Configure SGIs as standard interrupts In-Reply-To: References: <20200901144324.1071694-1-maz@kernel.org> <20200901144324.1071694-9-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26.3 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: james.morse@arm.com, jonathanh@nvidia.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sumit.garg@linaro.org, kernel-team@android.com, f.fainelli@gmail.com, linux@arm.linux.org.uk, jason@lakedaemon.net, saravanak@google.com, andrew@lunn.ch, catalin.marinas@arm.com, gregory.clement@bootlin.com, tglx@linutronix.de, will@kernel.org, valentin.schneider@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200918_062204_329197_5B67BFB6 X-CRM114-Status: GOOD ( 31.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sumit Garg , Florian Fainelli , Russell King , Jason Cooper , Saravana Kannan , Andrew Lunn , Catalin Marinas , Gregory Clement , linux-kernel@vger.kernel.org, jonathanh@nvidia.com, Will Deacon , Thomas Gleixner , kernel-team@android.com, Valentin Schneider , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi James, On Fri, 18 Sep 2020 10:58:45 +0100, James Morse wrote: > > Hi Marc, > > (CC: +Jon) > > On 01/09/2020 15:43, Marc Zyngier wrote: > > Change the way we deal with GIC SGIs by turning them into proper > > IRQs, and calling into the arch code to register the interrupt range > > instead of a callback. > > Your comment "This only works because we don't nest SGIs..." on this > thread tripped some bad memories from adding the irq-stack. Softirq > causes us to nest irqs, but only once. > > > (I've messed with the below diff to remove the added stuff:) > > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c > > index 4ffd62af888f..4be2b62f816f 100644 > > --- a/drivers/irqchip/irq-gic.c > > +++ b/drivers/irqchip/irq-gic.c > > @@ -335,31 +335,22 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) > > irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); > > irqnr = irqstat & GICC_IAR_INT_ID_MASK; > > > > - if (likely(irqnr > 15 && irqnr < 1020)) { > > - if (static_branch_likely(&supports_deactivate_key)) > > - writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); > > - isb(); > > - handle_domain_irq(gic->domain, irqnr, regs); > > - continue; > > - } > > - if (irqnr < 16) { > > writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); > > - if (static_branch_likely(&supports_deactivate_key)) > > - writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); > > -#ifdef CONFIG_SMP > > - /* > > - * Ensure any shared data written by the CPU sending > > - * the IPI is read after we've read the ACK register > > - * on the GIC. > > - * > > - * Pairs with the write barrier in gic_raise_softirq > > - */ > > smp_rmb(); > > - handle_IPI(irqnr, regs); > > If I read this right, previously we would EOI the interrupt before > calling handle_IPI(). Where as now with the version of this series > in your tree, we stuff the to-be-EOId value in a percpu variable, > which is only safe if these don't nest. > > Hidden in irq_exit(), kernel/softirq.c::__irq_exit_rcu() has this: > | preempt_count_sub(HARDIRQ_OFFSET); > | if (!in_interrupt() && local_softirq_pending()) > | invoke_softirq(); > > The arch code doesn't raise the preempt counter by HARDIRQ, so once > __irq_exit_rcu() has dropped it, in_interrupt() returns false, and > we invoke_softirq(). > > invoke_softirq() -> __do_softirq() -> local_irq_enable()! > > Fortunately, __do_softirq() raises the softirq count first using > __local_bh_disable_ip(), which in-interrupt() checks too, so this > can only happen once per IRQ. > > Now the irq_exit() has moved from handle_IPI(), which ran after EOI, > into handle_domain_irq(), which runs before. I think its possible > SGIs nest, and the new percpu variable becomes corrupted. I can't see how. The interrupt is active until we EOI/deactivate it, and thus cannot be observed again by the CPU interface until this happens. Furthermore, irq_exit() in __handle_domain_irq() is *after* the EOI anyway (generic_handle_irq_() directly calls the flow, which immediately EOIs the interrupt). The only material change is that irq_enter() happens before EOI. Is that what you are referring to? Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel