From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33258) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aGUgq-0006Su-9K for qemu-devel@nongnu.org; Tue, 05 Jan 2016 11:42:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aGUgk-0005GE-ED for qemu-devel@nongnu.org; Tue, 05 Jan 2016 11:42:32 -0500 Received: from mail-wm0-x235.google.com ([2a00:1450:400c:c09::235]:37114) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aGUgj-0005G6-Tx for qemu-devel@nongnu.org; Tue, 05 Jan 2016 11:42:26 -0500 Received: by mail-wm0-x235.google.com with SMTP id f206so37908852wmf.0 for ; Tue, 05 Jan 2016 08:42:25 -0800 (PST) References: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> <1450082498-27109-4-git-send-email-a.rigo@virtualopensystems.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1450082498-27109-4-git-send-email-a.rigo@virtualopensystems.com> Date: Tue, 05 Jan 2016 16:42:23 +0000 Message-ID: <87h9isc70w.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC v6 03/14] Add CPUClass hook to set exclusive range List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alvise Rigo Cc: mttcg@listserver.greensocs.com, claudio.fontana@huawei.com, qemu-devel@nongnu.org, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, rth@twiddle.net Alvise Rigo writes: > Allow each architecture to set the exclusive range at any LoadLink > operation through a CPUClass hook. nit: space or continue paragraph. > This comes in handy to emulate, for instance, the exclusive monitor > implemented in some ARM architectures (more precisely, the Exclusive > Reservation Granule). > > Suggested-by: Jani Kokkonen > Suggested-by: Claudio Fontana > Signed-off-by: Alvise Rigo Reviewed-by: Alex Bennée > --- > include/qom/cpu.h | 4 ++++ > qom/cpu.c | 7 +++++++ > 2 files changed, 11 insertions(+) > > diff --git a/include/qom/cpu.h b/include/qom/cpu.h > index c6bb6b6..9e409ce 100644 > --- a/include/qom/cpu.h > +++ b/include/qom/cpu.h > @@ -175,6 +175,10 @@ typedef struct CPUClass { > void (*cpu_exec_exit)(CPUState *cpu); > bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); > > + /* Atomic instruction handling */ > + void (*cpu_set_excl_protected_range)(CPUState *cpu, hwaddr addr, > + hwaddr size); > + > void (*disas_set_info)(CPUState *cpu, disassemble_info *info); > } CPUClass; > > diff --git a/qom/cpu.c b/qom/cpu.c > index fb80d13..a5c25a8 100644 > --- a/qom/cpu.c > +++ b/qom/cpu.c > @@ -203,6 +203,12 @@ static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) > return false; > } > > +static void cpu_common_set_excl_range(CPUState *cpu, hwaddr addr, hwaddr size) > +{ > + cpu->excl_protected_range.begin = addr; > + cpu->excl_protected_range.end = addr + size; > +} > + > void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, > int flags) > { > @@ -355,6 +361,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) > k->cpu_exec_enter = cpu_common_noop; > k->cpu_exec_exit = cpu_common_noop; > k->cpu_exec_interrupt = cpu_common_exec_interrupt; > + k->cpu_set_excl_protected_range = cpu_common_set_excl_range; > dc->realize = cpu_common_realizefn; > /* > * Reason: CPUs still need special care by board code: wiring up -- Alex Bennée