From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vagrant Cascadian Date: Wed, 12 Apr 2017 15:07:13 -0700 Subject: [U-Boot] [U-Boot, v6, 2/3] mmc: meson: add MMC driver for Meson GX (S905) In-Reply-To: <84b1742e-57b5-300b-c576-dbbe3d11b32a@gmail.com> References: <84b1742e-57b5-300b-c576-dbbe3d11b32a@gmail.com> Message-ID: <87inm9mga6.fsf@aikidev.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de On 2017-02-20, Heiner Kallweit wrote: > From: Carlo Caione > This driver implements MMC support on Meson GX (S905) based systems. > It's based on Carlo Caione's work, changes: > - BLK support added > - general refactoring > > Signed-off-by: Carlo Caione > Signed-off-by: Andreas F=C3=A4rber > Signed-off-by: Heiner Kallweit Tested loading a kernel+initrd+devicetree from mmc on an odroid-c2. Tested-by: Vagrant Cascadian > --- > v6: > - remove DM_MMC_OPS from Kconfig dependencies > - address two minor review comments of Jaehoon > --- > arch/arm/include/asm/arch-meson/sd_emmc.h | 89 +++++++++ > drivers/mmc/Kconfig | 6 + > drivers/mmc/Makefile | 1 + > drivers/mmc/meson_gx_mmc.c | 291 ++++++++++++++++++++++++= ++++++ > 4 files changed, 387 insertions(+) > create mode 100644 arch/arm/include/asm/arch-meson/sd_emmc.h > create mode 100644 drivers/mmc/meson_gx_mmc.c > > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include= /asm/arch-meson/sd_emmc.h > new file mode 100644 > index 0000000..a09e034 > --- /dev/null > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h > @@ -0,0 +1,89 @@ > +/* > + * (C) Copyright 2016 Carlo Caione > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __SD_EMMC_H__ > +#define __SD_EMMC_H__ > + > +#include > + > +#define SDIO_PORT_A 0 > +#define SDIO_PORT_B 1 > +#define SDIO_PORT_C 2 > + > +#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ > +#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ > + > +#define MESON_SD_EMMC_CLOCK 0x00 > +#define CLK_MAX_DIV 63 > +#define CLK_SRC_24M (0 << 6) > +#define CLK_SRC_DIV2 (1 << 6) > +#define CLK_CO_PHASE_000 (0 << 8) > +#define CLK_CO_PHASE_090 (1 << 8) > +#define CLK_CO_PHASE_180 (2 << 8) > +#define CLK_CO_PHASE_270 (3 << 8) > +#define CLK_TX_PHASE_000 (0 << 10) > +#define CLK_TX_PHASE_090 (1 << 10) > +#define CLK_TX_PHASE_180 (2 << 10) > +#define CLK_TX_PHASE_270 (3 << 10) > +#define CLK_ALWAYS_ON BIT(24) > + > +#define MESON_SD_EMMC_CFG 0x44 > +#define CFG_BUS_WIDTH_MASK GENMASK(1, 0) > +#define CFG_BUS_WIDTH_1 0 > +#define CFG_BUS_WIDTH_4 1 > +#define CFG_BUS_WIDTH_8 2 > +#define CFG_BL_LEN_MASK GENMASK(7, 4) > +#define CFG_BL_LEN_SHIFT 4 > +#define CFG_BL_LEN_512 (9 << 4) > +#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) > +#define CFG_RESP_TIMEOUT_256 (8 << 8) > +#define CFG_RC_CC_MASK GENMASK(15, 12) > +#define CFG_RC_CC_16 (4 << 12) > +#define CFG_SDCLK_ALWAYS_ON BIT(18) > +#define CFG_AUTO_CLK BIT(23) > + > +#define MESON_SD_EMMC_STATUS 0x48 > +#define STATUS_MASK GENMASK(15, 0) > +#define STATUS_ERR_MASK GENMASK(12, 0) > +#define STATUS_RXD_ERR_MASK GENMASK(7, 0) > +#define STATUS_TXD_ERR BIT(8) > +#define STATUS_DESC_ERR BIT(9) > +#define STATUS_RESP_ERR BIT(10) > +#define STATUS_RESP_TIMEOUT BIT(11) > +#define STATUS_DESC_TIMEOUT BIT(12) > +#define STATUS_END_OF_CHAIN BIT(13) > + > +#define MESON_SD_EMMC_IRQ_EN 0x4c > + > +#define MESON_SD_EMMC_CMD_CFG 0x50 > +#define CMD_CFG_LENGTH_MASK GENMASK(8, 0) > +#define CMD_CFG_BLOCK_MODE BIT(9) > +#define CMD_CFG_R1B BIT(10) > +#define CMD_CFG_END_OF_CHAIN BIT(11) > +#define CMD_CFG_TIMEOUT_4S (12 << 12) > +#define CMD_CFG_NO_RESP BIT(16) > +#define CMD_CFG_DATA_IO BIT(18) > +#define CMD_CFG_DATA_WR BIT(19) > +#define CMD_CFG_RESP_NOCRC BIT(20) > +#define CMD_CFG_RESP_128 BIT(21) > +#define CMD_CFG_CMD_INDEX_SHIFT 24 > +#define CMD_CFG_OWNER BIT(31) > + > +#define MESON_SD_EMMC_CMD_ARG 0x54 > +#define MESON_SD_EMMC_CMD_DAT 0x58 > +#define MESON_SD_EMMC_CMD_RSP 0x5c > +#define MESON_SD_EMMC_CMD_RSP1 0x60 > +#define MESON_SD_EMMC_CMD_RSP2 0x64 > +#define MESON_SD_EMMC_CMD_RSP3 0x68 > + > +struct meson_mmc_platdata { > + struct mmc_config cfg; > + struct mmc mmc; > + void *regbase; > + void *w_buf; > +}; > + > +#endif > diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig > index 01d1dbf..aedd7a7 100644 > --- a/drivers/mmc/Kconfig > +++ b/drivers/mmc/Kconfig > @@ -105,6 +105,12 @@ config MMC_DW_SOCFPGA > Synopsys DesignWare Memory Card Interface driver. Select this option > for platforms based on Altera SOCFPGA. > =20 > +config MMC_MESON_GX > + bool "Meson GX EMMC controller support" > + depends on DM_MMC && BLK && ARCH_MESON > + help > + Support for EMMC host controller on Meson GX ARM SoCs platform (S905) > + > config MMC_MXC > bool "Freescale i.MX21/27/31 or MPC512x Multimedia Card support" > help > diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile > index 8e922db..a0c9daf 100644 > --- a/drivers/mmc/Makefile > +++ b/drivers/mmc/Makefile > @@ -29,6 +29,7 @@ ifdef CONFIG_SUPPORT_EMMC_BOOT > obj-$(CONFIG_GENERIC_MMC) +=3D mmc_boot.o > endif > obj-$(CONFIG_GENERIC_ATMEL_MCI) +=3D gen_atmel_mci.o > +obj-$(CONFIG_MMC_MESON_GX) +=3D meson_gx_mmc.o > obj-$(CONFIG_MMC_SPI) +=3D mmc_spi.o > obj-$(CONFIG_MVEBU_MMC) +=3D mvebu_mmc.o > obj-$(CONFIG_MMC_OMAP_HS) +=3D omap_hsmmc.o > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c > new file mode 100644 > index 0000000..8e28ab7 > --- /dev/null > +++ b/drivers/mmc/meson_gx_mmc.c > @@ -0,0 +1,291 @@ > +/* > + * (C) Copyright 2016 Carlo Caione > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +static inline void *get_regbase(const struct mmc *mmc) > +{ > + struct meson_mmc_platdata *pdata =3D mmc->priv; > + > + return pdata->regbase; > +} > + > +static inline uint32_t meson_read(struct mmc *mmc, int offset) > +{ > + return readl(get_regbase(mmc) + offset); > +} > + > +static inline void meson_write(struct mmc *mmc, uint32_t val, int offset) > +{ > + writel(val, get_regbase(mmc) + offset); > +} > + > +static void meson_mmc_config_clock(struct mmc *mmc) > +{ > + uint32_t meson_mmc_clk =3D 0; > + unsigned int clk, clk_src, clk_div; > + > + /* 1GHz / CLK_MAX_DIV =3D 15,9 MHz */ > + if (mmc->clock > 16000000) { > + clk =3D SD_EMMC_CLKSRC_DIV2; > + clk_src =3D CLK_SRC_DIV2; > + } else { > + clk =3D SD_EMMC_CLKSRC_24M; > + clk_src =3D CLK_SRC_24M; > + } > + clk_div =3D DIV_ROUND_UP(clk, mmc->clock); > + > + /* 180 phase core clock */ > + meson_mmc_clk |=3D CLK_CO_PHASE_180; > + > + /* 180 phase tx clock */ > + meson_mmc_clk |=3D CLK_TX_PHASE_000; > + > + /* clock settings */ > + meson_mmc_clk |=3D clk_src; > + meson_mmc_clk |=3D clk_div; > + > + meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK); > +} > + > +static int meson_dm_mmc_set_ios(struct udevice *dev) > +{ > + struct mmc *mmc =3D mmc_get_mmc_dev(dev); > + uint32_t meson_mmc_cfg; > + > + meson_mmc_config_clock(mmc); > + > + meson_mmc_cfg =3D meson_read(mmc, MESON_SD_EMMC_CFG); > + > + meson_mmc_cfg &=3D ~CFG_BUS_WIDTH_MASK; > + if (mmc->bus_width =3D=3D 1) > + meson_mmc_cfg |=3D CFG_BUS_WIDTH_1; > + else if (mmc->bus_width =3D=3D 4) > + meson_mmc_cfg |=3D CFG_BUS_WIDTH_4; > + else if (mmc->bus_width =3D=3D 8) > + meson_mmc_cfg |=3D CFG_BUS_WIDTH_8; > + else > + return -EINVAL; > + > + /* 512 bytes block length */ > + meson_mmc_cfg &=3D ~CFG_BL_LEN_MASK; > + meson_mmc_cfg |=3D CFG_BL_LEN_512; > + > + /* Response timeout 256 clk */ > + meson_mmc_cfg &=3D ~CFG_RESP_TIMEOUT_MASK; > + meson_mmc_cfg |=3D CFG_RESP_TIMEOUT_256; > + > + /* Command-command gap 16 clk */ > + meson_mmc_cfg &=3D ~CFG_RC_CC_MASK; > + meson_mmc_cfg |=3D CFG_RC_CC_16; > + > + meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG); > + > + return 0; > +} > + > +static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data, > + struct mmc_cmd *cmd) > +{ > + uint32_t meson_mmc_cmd =3D 0, cfg; > + > + meson_mmc_cmd |=3D cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT; > + > + if (cmd->resp_type & MMC_RSP_PRESENT) { > + if (cmd->resp_type & MMC_RSP_136) > + meson_mmc_cmd |=3D CMD_CFG_RESP_128; > + > + if (cmd->resp_type & MMC_RSP_BUSY) > + meson_mmc_cmd |=3D CMD_CFG_R1B; > + > + if (!(cmd->resp_type & MMC_RSP_CRC)) > + meson_mmc_cmd |=3D CMD_CFG_RESP_NOCRC; > + } else { > + meson_mmc_cmd |=3D CMD_CFG_NO_RESP; > + } > + > + if (data) { > + cfg =3D meson_read(mmc, MESON_SD_EMMC_CFG); > + cfg &=3D ~CFG_BL_LEN_MASK; > + cfg |=3D ilog2(data->blocksize) << CFG_BL_LEN_SHIFT; > + meson_write(mmc, cfg, MESON_SD_EMMC_CFG); > + > + if (data->flags =3D=3D MMC_DATA_WRITE) > + meson_mmc_cmd |=3D CMD_CFG_DATA_WR; > + > + meson_mmc_cmd |=3D CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE | > + data->blocks; > + } > + > + meson_mmc_cmd |=3D CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER | > + CMD_CFG_END_OF_CHAIN; > + > + meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG); > +} > + > +static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data) > +{ > + struct meson_mmc_platdata *pdata =3D mmc->priv; > + unsigned int data_size; > + uint32_t data_addr =3D 0; > + > + if (data) { > + data_size =3D data->blocks * data->blocksize; > + > + if (data->flags =3D=3D MMC_DATA_READ) { > + data_addr =3D (ulong) data->dest; > + invalidate_dcache_range(data_addr, > + data_addr + data_size); > + } else { > + pdata->w_buf =3D calloc(data_size, sizeof(char)); > + data_addr =3D (ulong) pdata->w_buf; > + memcpy(pdata->w_buf, data->src, data_size); > + flush_dcache_range(data_addr, data_addr + data_size); > + } > + } > + > + meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT); > +} > + > +static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd) > +{ > + if (cmd->resp_type & MMC_RSP_136) { > + cmd->response[0] =3D meson_read(mmc, MESON_SD_EMMC_CMD_RSP3); > + cmd->response[1] =3D meson_read(mmc, MESON_SD_EMMC_CMD_RSP2); > + cmd->response[2] =3D meson_read(mmc, MESON_SD_EMMC_CMD_RSP1); > + cmd->response[3] =3D meson_read(mmc, MESON_SD_EMMC_CMD_RSP); > + } else { > + cmd->response[0] =3D meson_read(mmc, MESON_SD_EMMC_CMD_RSP); > + } > +} > + > +static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cm= d, > + struct mmc_data *data) > +{ > + struct mmc *mmc =3D mmc_get_mmc_dev(dev); > + struct meson_mmc_platdata *pdata =3D mmc->priv; > + uint32_t status; > + ulong start; > + int ret =3D 0; > + > + /* max block size supported by chip is 512 byte */ > + if (data && data->blocksize > 512) > + return -EINVAL; > + > + meson_mmc_setup_cmd(mmc, data, cmd); > + meson_mmc_setup_addr(mmc, data); > + > + meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG); > + > + /* use 10s timeout */ > + start =3D get_timer(0); > + do { > + status =3D meson_read(mmc, MESON_SD_EMMC_STATUS); > + } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000); > + > + if (!(status & STATUS_END_OF_CHAIN)) > + ret =3D -ETIMEDOUT; > + else if (status & STATUS_RESP_TIMEOUT) > + ret =3D -ETIMEDOUT; > + else if (status & STATUS_ERR_MASK) > + ret =3D -EIO; > + > + meson_mmc_read_response(mmc, cmd); > + > + if (data && data->flags =3D=3D MMC_DATA_WRITE) > + free(pdata->w_buf); > + > + /* reset status bits */ > + meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS); > + > + return ret; > +} > + > +static const struct dm_mmc_ops meson_dm_mmc_ops =3D { > + .send_cmd =3D meson_dm_mmc_send_cmd, > + .set_ios =3D meson_dm_mmc_set_ios, > +}; > + > +static int meson_mmc_ofdata_to_platdata(struct udevice *dev) > +{ > + struct meson_mmc_platdata *pdata =3D dev_get_platdata(dev); > + fdt_addr_t addr; > + > + addr =3D dev_get_addr(dev); > + if (addr =3D=3D FDT_ADDR_T_NONE) > + return -EINVAL; > + > + pdata->regbase =3D (void *)addr; > + > + return 0; > +} > + > +static int meson_mmc_probe(struct udevice *dev) > +{ > + struct meson_mmc_platdata *pdata =3D dev_get_platdata(dev); > + struct mmc_uclass_priv *upriv =3D dev_get_uclass_priv(dev); > + struct mmc *mmc =3D &pdata->mmc; > + struct mmc_config *cfg =3D &pdata->cfg; > + uint32_t val; > + > + cfg->voltages =3D MMC_VDD_33_34 | MMC_VDD_32_33 | > + MMC_VDD_31_32 | MMC_VDD_165_195; > + cfg->host_caps =3D MMC_MODE_8BIT | MMC_MODE_4BIT | > + MMC_MODE_HS_52MHz | MMC_MODE_HS; > + cfg->f_min =3D DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV); > + cfg->f_max =3D 100000000; /* 100 MHz */ > + cfg->b_max =3D 256; /* max 256 blocks */ > + cfg->name =3D dev->name; > + > + mmc->priv =3D pdata; > + upriv->mmc =3D mmc; > + > + mmc_set_clock(mmc, cfg->f_min); > + > + /* reset all status bits */ > + meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS); > + > + /* disable interrupts */ > + meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN); > + > + /* enable auto clock mode */ > + val =3D meson_read(mmc, MESON_SD_EMMC_CFG); > + val &=3D ~CFG_SDCLK_ALWAYS_ON; > + val |=3D CFG_AUTO_CLK; > + meson_write(mmc, val, MESON_SD_EMMC_CFG); > + > + return 0; > +} > + > +int meson_mmc_bind(struct udevice *dev) > +{ > + struct meson_mmc_platdata *pdata =3D dev_get_platdata(dev); > + > + return mmc_bind(dev, &pdata->mmc, &pdata->cfg); > +} > + > +static const struct udevice_id meson_mmc_match[] =3D { > + { .compatible =3D "amlogic,meson-gx-mmc" }, > + { /* sentinel */ } > +}; > + > +U_BOOT_DRIVER(meson_mmc) =3D { > + .name =3D "meson_gx_mmc", > + .id =3D UCLASS_MMC, > + .of_match =3D meson_mmc_match, > + .ops =3D &meson_dm_mmc_ops, > + .probe =3D meson_mmc_probe, > + .bind =3D meson_mmc_bind, > + .ofdata_to_platdata =3D meson_mmc_ofdata_to_platdata, > + .platdata_auto_alloc_size =3D sizeof(struct meson_mmc_platdata), > +}; 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