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From: Leon Schuermann <leon@is.currently.online>
To: qemu-riscv@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>
Subject: Re: [PATCH] target/riscv/pmp: fix non-translated page size address checks w/ MPU
Date: Tue, 06 Sep 2022 10:45:46 -0400	[thread overview]
Message-ID: <87k06ga7dx.fsf@silicon.host.schuermann.io> (raw)
In-Reply-To: <20220904192907.1056740-1-leon@is.currently.online>

leon@is.currently.online writes:
> While there possibly are other unhandled edge cases in which
> page-granularity access checks might not be appropriate, this commit
> appears to be a strict improvement over the current implementation's
> behavior.

One particular example of an additional edge case might be a hart
operating in M-mode. Given that virtual memory through
{Sv32,Sv39,Sv48,Sv57} is only supported for S-mode and U-mode
respectively, enabling virtual memory in the satp CSR should not have
any effect on the behavior of memory accesses w.r.t. PMP checks for
harts operating in M-mode.

I'm going to defer adding this additional check, as I'd appreciate some
feedback as to whether my reasoning is correct here at all first.

Thanks!

-Leon


  reply	other threads:[~2022-09-06 14:46 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-04 19:29 [PATCH] target/riscv/pmp: fix non-translated page size address checks w/ MPU leon
2022-09-06 14:45 ` Leon Schuermann [this message]
2022-09-09 15:22 leon
2022-09-19 23:28 ` Alistair Francis
2022-10-19 21:29   ` Leon Schuermann
2022-10-25  2:19     ` Alistair Francis

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