From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ECBCC47094 for ; Mon, 7 Jun 2021 16:35:30 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 221C561E61 for ; Mon, 7 Jun 2021 16:35:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 221C561E61 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id A53FE4B089; Mon, 7 Jun 2021 12:35:29 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id djJPSRfwocYL; Mon, 7 Jun 2021 12:35:25 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 0084E4AEE2; Mon, 7 Jun 2021 12:35:25 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 9783F4A531 for ; Mon, 7 Jun 2021 12:35:23 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dXU6jbjGaHFy for ; Mon, 7 Jun 2021 12:35:19 -0400 (EDT) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id A8F514A523 for ; Mon, 7 Jun 2021 12:35:19 -0400 (EDT) Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6D1956136D; Mon, 7 Jun 2021 16:35:18 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1lqIDc-005zvV-D8; Mon, 07 Jun 2021 17:35:16 +0100 Date: Mon, 07 Jun 2021 17:35:15 +0100 Message-ID: <87lf7lzl8c.wl-maz@kernel.org> From: Marc Zyngier To: "Jain, Jinank" Subject: Re: [PATCH] KVM: arm64: Properly restore PMU state during live-migration In-Reply-To: <0a694ea93303bfa04530cd940f692244e1ccd1e7.camel@amazon.de> References: <20210603110554.13643-1-jinankj@amazon.de> <87wnrbylxv.wl-maz@kernel.org> <0a694ea93303bfa04530cd940f692244e1ccd1e7.camel@amazon.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: jinankj@amazon.de, james.morse@arm.com, kvmarm@lists.cs.columbia.edu, suzuki.poulose@arm.com, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, will@kernel.org, alexandru.elisei@arm.com, graf@amazon.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: "Graf \(AWS\), Alexander" , "catalin.marinas@arm.com" , "linux-kernel@vger.kernel.org" , "will@kernel.org" , "kvmarm@lists.cs.columbia.edu" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Mon, 07 Jun 2021 17:05:01 +0100, "Jain, Jinank" wrote: > > On Thu, 2021-06-03 at 17:03 +0100, Marc Zyngier wrote: > > > > Hi Jinank, > > > > On Thu, 03 Jun 2021 12:05:54 +0100, > > Jinank Jain wrote: > > > Currently if a guest is live-migrated while it is actively using > > > perf > > > counters, then after live-migrate it will notice that all counters > > > would > > > suddenly start reporting 0s. This is due to the fact we are not > > > re-creating the relevant perf events inside the kernel. > > > > > > Usually on live-migration guest state is restored using > > > KVM_SET_ONE_REG > > > ioctl interface, which simply restores the value of PMU registers > > > values but does not re-program the perf events so that the guest > > > can seamlessly > > > use these counters even after live-migration like it was doing > > > before > > > live-migration. > > > > > > Instead there are two completely different code path between guest > > > accessing PMU registers and VMM restoring counters on > > > live-migration. > > > > > > In case of KVM_SET_ONE_REG: > > > > > > kvm_arm_set_reg() > > > ...... kvm_arm_sys_reg_set_reg() > > > ........... reg_from_user() > > > > > > but in case when guest tries to access these counters: > > > > > > handle_exit() > > > ..... kvm_handle_sys_reg() > > > ..........perform_access() > > > ...............access_pmu_evcntr() > > > ...................kvm_pmu_set_counter_value() > > > .......................kvm_pmu_create_perf_event() > > > > > > The drawback of using the KVM_SET_ONE_REG interface is that the > > > host pmu > > > events which were registered for the source instance and not > > > present for > > > the destination instance. > > > > I can't parse this sentence. Do you mean "are not present"? > > > > > Thus passively restoring PMCR_EL0 using > > > KVM_SET_ONE_REG interface would not create the necessary host pmu > > > events > > > which are crucial for seamless guest experience across live > > > migration. > > > > > > In ordet to fix the situation, on first vcpu load we should restore > > > PMCR_EL0 in the same exact way like the guest was trying to access > > > these counters. And then we will also recreate the relevant host > > > pmu > > > events. > > > > > > Signed-off-by: Jinank Jain > > > Cc: Alexander Graf (AWS) > > > Cc: Marc Zyngier > > > Cc: James Morse > > > Cc: Alexandru Elisei > > > Cc: Suzuki K Poulose > > > Cc: Catalin Marinas > > > Cc: Will Deacon > > > --- > > > arch/arm64/include/asm/kvm_host.h | 1 + > > > arch/arm64/kvm/arm.c | 1 + > > > arch/arm64/kvm/pmu-emul.c | 10 ++++++++-- > > > arch/arm64/kvm/pmu.c | 15 +++++++++++++++ > > > include/kvm/arm_pmu.h | 3 +++ > > > 5 files changed, 28 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/arm64/include/asm/kvm_host.h > > > b/arch/arm64/include/asm/kvm_host.h > > > index 7cd7d5c8c4bc..2376ad3c2fc2 100644 > > > --- a/arch/arm64/include/asm/kvm_host.h > > > +++ b/arch/arm64/include/asm/kvm_host.h > > > @@ -745,6 +745,7 @@ static inline int > > > kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) > > > void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); > > > void kvm_clr_pmu_events(u32 clr); > > > > > > +void kvm_vcpu_pmu_restore(struct kvm_vcpu *vcpu); > > > void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); > > > void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); > > > #else > > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > > > index e720148232a0..c66f6d16ec06 100644 > > > --- a/arch/arm64/kvm/arm.c > > > +++ b/arch/arm64/kvm/arm.c > > > @@ -408,6 +408,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, > > > int cpu) > > > if (has_vhe()) > > > kvm_vcpu_load_sysregs_vhe(vcpu); > > > kvm_arch_vcpu_load_fp(vcpu); > > > + kvm_vcpu_pmu_restore(vcpu); > > > > If this only needs to be run once per vcpu, why not trigger it from > > kvm_arm_pmu_v3_enable(), which is also called once per vcpu? > > > > This can done on the back of a request, saving most of the overhead > > and not requiring any extra field. Essentially, something like the > > (untested) patch below. > > > > > kvm_vcpu_pmu_restore_guest(vcpu); > > > if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) > > > kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); > > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > > > index fd167d4f4215..12a40f4b5f0d 100644 > > > --- a/arch/arm64/kvm/pmu-emul.c > > > +++ b/arch/arm64/kvm/pmu-emul.c > > > @@ -574,10 +574,16 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu > > > *vcpu, u64 val) > > > kvm_pmu_disable_counter_mask(vcpu, mask); > > > } > > > > > > - if (val & ARMV8_PMU_PMCR_C) > > > + /* > > > + * Cycle counter needs to reset in case of first vcpu load. > > > + */ > > > + if (val & ARMV8_PMU_PMCR_C || !kvm_arm_pmu_v3_restored(vcpu)) > > > > Why? There is no architectural guarantee that a counter resets to 0 > > without writing PMCR_EL0.C. And if you want the guest to continue > > counting where it left off, resetting the counter is at best > > counter-productive. > > Without this we would not be resetting PMU which is required for > creating host perf events. With the patch that you suggested we are > restoring PMCR_EL0 properly but still missing recreation of host perf > events. How? The request that gets set on the first vcpu run will call kvm_pmu_handle_pmcr() -> kvm_pmu_enable_counter_mask() -> kvm_pmu_create_perf_event(). What are we missing? > And without host perf events, guest would still zeros after live > migration. In my opinion we have two ways to fix it. We can fix it > inside the kernel or let userspace/VMM set those bits before > restarting the guest on the destination machine. What do you think? I think either you're missing my point above, or I'm completely missing yours. And I still don't understand why you want to zero the counters that you have just restored. How does that help? M. -- Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23FB1C47082 for ; Mon, 7 Jun 2021 16:47:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E69BA60FDA for ; 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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqINw-004aV6-6L; Mon, 07 Jun 2021 16:45:56 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lqIDf-004Xs2-WF for linux-arm-kernel@lists.infradead.org; Mon, 07 Jun 2021 16:35:23 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6D1956136D; Mon, 7 Jun 2021 16:35:18 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1lqIDc-005zvV-D8; Mon, 07 Jun 2021 17:35:16 +0100 Date: Mon, 07 Jun 2021 17:35:15 +0100 Message-ID: <87lf7lzl8c.wl-maz@kernel.org> From: Marc Zyngier To: "Jain, Jinank" Cc: "james.morse@arm.com" , "kvmarm@lists.cs.columbia.edu" , "suzuki.poulose@arm.com" , "linux-kernel@vger.kernel.org" , "catalin.marinas@arm.com" , "linux-arm-kernel@lists.infradead.org" , "will@kernel.org" , "alexandru.elisei@arm.com" , "Graf (AWS),\ Alexander" Subject: Re: [PATCH] KVM: arm64: Properly restore PMU state during live-migration In-Reply-To: <0a694ea93303bfa04530cd940f692244e1ccd1e7.camel@amazon.de> References: <20210603110554.13643-1-jinankj@amazon.de> <87wnrbylxv.wl-maz@kernel.org> <0a694ea93303bfa04530cd940f692244e1ccd1e7.camel@amazon.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: jinankj@amazon.de, james.morse@arm.com, kvmarm@lists.cs.columbia.edu, suzuki.poulose@arm.com, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, will@kernel.org, alexandru.elisei@arm.com, graf@amazon.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210607_093520_128419_5FB5D8C5 X-CRM114-Status: GOOD ( 49.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 07 Jun 2021 17:05:01 +0100, "Jain, Jinank" wrote: > > On Thu, 2021-06-03 at 17:03 +0100, Marc Zyngier wrote: > > > > Hi Jinank, > > > > On Thu, 03 Jun 2021 12:05:54 +0100, > > Jinank Jain wrote: > > > Currently if a guest is live-migrated while it is actively using > > > perf > > > counters, then after live-migrate it will notice that all counters > > > would > > > suddenly start reporting 0s. This is due to the fact we are not > > > re-creating the relevant perf events inside the kernel. > > > > > > Usually on live-migration guest state is restored using > > > KVM_SET_ONE_REG > > > ioctl interface, which simply restores the value of PMU registers > > > values but does not re-program the perf events so that the guest > > > can seamlessly > > > use these counters even after live-migration like it was doing > > > before > > > live-migration. > > > > > > Instead there are two completely different code path between guest > > > accessing PMU registers and VMM restoring counters on > > > live-migration. > > > > > > In case of KVM_SET_ONE_REG: > > > > > > kvm_arm_set_reg() > > > ...... kvm_arm_sys_reg_set_reg() > > > ........... reg_from_user() > > > > > > but in case when guest tries to access these counters: > > > > > > handle_exit() > > > ..... kvm_handle_sys_reg() > > > ..........perform_access() > > > ...............access_pmu_evcntr() > > > ...................kvm_pmu_set_counter_value() > > > .......................kvm_pmu_create_perf_event() > > > > > > The drawback of using the KVM_SET_ONE_REG interface is that the > > > host pmu > > > events which were registered for the source instance and not > > > present for > > > the destination instance. > > > > I can't parse this sentence. Do you mean "are not present"? > > > > > Thus passively restoring PMCR_EL0 using > > > KVM_SET_ONE_REG interface would not create the necessary host pmu > > > events > > > which are crucial for seamless guest experience across live > > > migration. > > > > > > In ordet to fix the situation, on first vcpu load we should restore > > > PMCR_EL0 in the same exact way like the guest was trying to access > > > these counters. And then we will also recreate the relevant host > > > pmu > > > events. > > > > > > Signed-off-by: Jinank Jain > > > Cc: Alexander Graf (AWS) > > > Cc: Marc Zyngier > > > Cc: James Morse > > > Cc: Alexandru Elisei > > > Cc: Suzuki K Poulose > > > Cc: Catalin Marinas > > > Cc: Will Deacon > > > --- > > > arch/arm64/include/asm/kvm_host.h | 1 + > > > arch/arm64/kvm/arm.c | 1 + > > > arch/arm64/kvm/pmu-emul.c | 10 ++++++++-- > > > arch/arm64/kvm/pmu.c | 15 +++++++++++++++ > > > include/kvm/arm_pmu.h | 3 +++ > > > 5 files changed, 28 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/arm64/include/asm/kvm_host.h > > > b/arch/arm64/include/asm/kvm_host.h > > > index 7cd7d5c8c4bc..2376ad3c2fc2 100644 > > > --- a/arch/arm64/include/asm/kvm_host.h > > > +++ b/arch/arm64/include/asm/kvm_host.h > > > @@ -745,6 +745,7 @@ static inline int > > > kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) > > > void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); > > > void kvm_clr_pmu_events(u32 clr); > > > > > > +void kvm_vcpu_pmu_restore(struct kvm_vcpu *vcpu); > > > void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); > > > void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); > > > #else > > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > > > index e720148232a0..c66f6d16ec06 100644 > > > --- a/arch/arm64/kvm/arm.c > > > +++ b/arch/arm64/kvm/arm.c > > > @@ -408,6 +408,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, > > > int cpu) > > > if (has_vhe()) > > > kvm_vcpu_load_sysregs_vhe(vcpu); > > > kvm_arch_vcpu_load_fp(vcpu); > > > + kvm_vcpu_pmu_restore(vcpu); > > > > If this only needs to be run once per vcpu, why not trigger it from > > kvm_arm_pmu_v3_enable(), which is also called once per vcpu? > > > > This can done on the back of a request, saving most of the overhead > > and not requiring any extra field. Essentially, something like the > > (untested) patch below. > > > > > kvm_vcpu_pmu_restore_guest(vcpu); > > > if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) > > > kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); > > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > > > index fd167d4f4215..12a40f4b5f0d 100644 > > > --- a/arch/arm64/kvm/pmu-emul.c > > > +++ b/arch/arm64/kvm/pmu-emul.c > > > @@ -574,10 +574,16 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu > > > *vcpu, u64 val) > > > kvm_pmu_disable_counter_mask(vcpu, mask); > > > } > > > > > > - if (val & ARMV8_PMU_PMCR_C) > > > + /* > > > + * Cycle counter needs to reset in case of first vcpu load. > > > + */ > > > + if (val & ARMV8_PMU_PMCR_C || !kvm_arm_pmu_v3_restored(vcpu)) > > > > Why? There is no architectural guarantee that a counter resets to 0 > > without writing PMCR_EL0.C. And if you want the guest to continue > > counting where it left off, resetting the counter is at best > > counter-productive. > > Without this we would not be resetting PMU which is required for > creating host perf events. With the patch that you suggested we are > restoring PMCR_EL0 properly but still missing recreation of host perf > events. How? The request that gets set on the first vcpu run will call kvm_pmu_handle_pmcr() -> kvm_pmu_enable_counter_mask() -> kvm_pmu_create_perf_event(). What are we missing? > And without host perf events, guest would still zeros after live > migration. In my opinion we have two ways to fix it. We can fix it > inside the kernel or let userspace/VMM set those bits before > restarting the guest on the destination machine. What do you think? I think either you're missing my point above, or I'm completely missing yours. And I still don't understand why you want to zero the counters that you have just restored. How does that help? M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel