From mboxrd@z Thu Jan  1 00:00:00 1970
From: Francisco Jerez <currojerez@riseup.net>
Subject: Re: [PATCH 3/5] drm/i915: Move Haswell registers to
	separate whitelist table
Date: Tue, 08 Mar 2016 14:05:29 -0800
Message-ID: <87lh5sfwwm.fsf@riseup.net>
References: <1457335830-30923-1-git-send-email-jordan.l.justen@intel.com>
 <1457335830-30923-4-git-send-email-jordan.l.justen@intel.com>
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Jordan Justen <jordan.l.justen@intel.com> writes:

> Now that we can whitelist registers only on Haswell, move HSW_SCRATCH1
> and HSW_ROW_CHICKEN3 into a separate Haswell only table.
>
> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Francisco Jerez <currojerez@riseup.net>

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i91=
5/i915_cmd_parser.c
> index 46ea40b..ba01836 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -472,6 +472,9 @@ static const struct drm_i915_reg_descriptor gen7_rend=
er_regs[] =3D {
>  	REG32(GEN7_L3SQCREG1),
>  	REG32(GEN7_L3CNTLREG2),
>  	REG32(GEN7_L3CNTLREG3),
> +};
> +
> +static const struct drm_i915_reg_descriptor hsw_render_regs[] =3D {
>  	REG32(HSW_SCRATCH1,
>  	      .mask =3D ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
>  	      .value =3D 0),
> @@ -519,6 +522,7 @@ static const struct drm_i915_reg_table ivb_blt_reg_ta=
bles[] =3D {
>=20=20
>  static const struct drm_i915_reg_table hsw_render_reg_tables[] =3D {
>  	{ gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
> +	{ hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
>  	{ hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
>  };
>=20=20
> --=20
> 2.7.0

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