From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5837C7EE23 for ; Thu, 1 Jun 2023 05:02:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231297AbjFAFCs (ORCPT ); Thu, 1 Jun 2023 01:02:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229603AbjFAFCq (ORCPT ); Thu, 1 Jun 2023 01:02:46 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99AAC12C for ; Wed, 31 May 2023 22:02:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 30EF263FC9 for ; Thu, 1 Jun 2023 05:02:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7FB11C433EF; Thu, 1 Jun 2023 05:02:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685595764; bh=zs1I394rk/Mw+oYwq8XKLNXM/rtn1y1wKjDBN5Wu3MM=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=siqfEj6c1V8QvOG2LpafSKdu3pq2p/RMWv3BrHquxF2BJ4xRahyb5wyQZlVBQJfYl 1fKnpO/xitKhnLsVyHpA8pzu47EdDtj/S8xKh7yVKmY8s7FQx/b2Xt8XEmHtqjuYPM W1DfsB0nwOCMK4m+ag2nV1Q6LMi1++502gA+svo49nRBTDE75jTsgiCKSiqk5XYNYJ f2W90MbSqMhqjksfMFeIGmYoisI7GOk51zdmjoV6JZma9fV2C5YKKBmYD9/G4y+gJY KYZqdV21rQ3gozntxPFSsgTsazqNLxBIwJ/1DvcfoQz5chxrTJz6al7v/QtdPq4DV4 b3UpskHgb4q/Q== Received: from [62.252.176.218] (helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1q4aSQ-001po8-4A; Thu, 01 Jun 2023 06:02:42 +0100 Date: Thu, 01 Jun 2023 06:02:41 +0100 Message-ID: <87mt1jkc5q.wl-maz@kernel.org> From: Marc Zyngier To: Reiji Watanabe Cc: Oliver Upton , kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Will Deacon Subject: Re: [PATCH 0/4] KVM: arm64: PMU: Fix PMUVer handling on heterogeneous PMU systems In-Reply-To: <20230530125324.ijrwrvoll2detpus@google.com> References: <20230527040236.1875860-1-reijiw@google.com> <87zg5njlyn.wl-maz@kernel.org> <20230530125324.ijrwrvoll2detpus@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.252.176.218 X-SA-Exim-Rcpt-To: reijiw@google.com, oliver.upton@linux.dev, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, alexandru.elisei@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, pbonzini@redhat.com, ricarkol@google.com, jingzhangos@google.com, rananta@google.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hey Reiji, On Tue, 30 May 2023 13:53:24 +0100, Reiji Watanabe wrote: > > Hi Marc, > > On Mon, May 29, 2023 at 02:39:28PM +0100, Marc Zyngier wrote: > > On Sat, 27 May 2023 05:02:32 +0100, > > Reiji Watanabe wrote: > > > > > > This series fixes issues with PMUVer handling for a guest with > > > PMU configured on heterogeneous PMU systems. > > > Specifically, it addresses the following two issues. > > > > > > [A] The default value of ID_AA64DFR0_EL1.PMUVer of the vCPU is set > > > to its sanitized value. This could be inappropriate on > > > heterogeneous PMU systems, as arm64_ftr_bits for PMUVer is defined > > > as FTR_EXACT with safe_val == 0 (when ID_AA64DFR0_EL1.PMUVer of all > > > PEs on the host is not uniform, the sanitized value will be 0). > > > > Why is this a problem? The CPUs don't implement the same version of > > the architecture, we don't get a PMU. Why should we try to do anything > > better? I really don't think we should go out or out way and make the > > code more complicated for something that doesn't really exist. > > Even when the CPUs don't implement the same version of the architecture, > if one of them implement PMUv3, KVM advertises KVM_CAP_ARM_PMU_V3, > and allows userspace to configure PMU (KVM_ARM_VCPU_PMU_V3) for vCPUs. Ah, I see it now. The kernel will register the PMU even if it decides that advertising it is wrong, and then we pick it up. Great :-/. > In this case, although KVM provides PMU emulations for the guest, > the guest's ID_AA64DFR0_EL1.PMUVer will be zero. Also, > KVM_SET_ONE_REG for ID_AA64DFR0_EL1 will never work for vCPUs > with PMU configured on such systems (since KVM also doesn't allow > userspace to set the PMUVer to 0 for the vCPUs with PMU configured). > > I would think either ID_AA64DFR0_EL1.PMUVer for the guest should > indicate PMUv3, or KVM should not allow userspace to configure PMU, > in this case. My vote is on the latter. Even if a PMU is available, we should rely on the feature exposed by the kernel to decide whether exposing a PMU or not. To be honest, this will affect almost nobody (I only know of a single one, an obscure ARMv8.0+ARMv8.2 system which is very unlikely to ever use KVM). I'm happy to take the responsibility to actively break those. > This series is a fix for the former, mainly to keep the current > behavior of KVM_CAP_ARM_PMU_V3 and KVM_ARM_VCPU_PMU_V3 on such > systems, since I wasn't sure if such systems don't really exist :) > (Also, I plan to implement a similar fix for PMCR_EL0.N on top of > those changes) > > I could make a fix for the latter instead though. What do you think ? I think this would be valuable. Also, didn't you have patches for the EL0 side of the PMU? I've been trying to look for a new version, but couldn't find it... Thanks, M. -- Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5DA1C7EE23 for ; Thu, 1 Jun 2023 05:03:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7XNbIxN6DEl53EtstKvsqilBAZNp6jlIBLRF9e0gObI=; b=Hv6nT+gYda7VVs zmKfw0c944whOZJa2cz+DdC/AFG2hOH1ujZaSmj5VecIB3qZSWDVuFToCzH74SwWxNOFqye0hD7Nu ruC9l1W44VFlFVIc/LPA6/PMxMgYVyvSLh+ObwIwUcuG7X+PYmKSXj7B1gXG+H6sukijgqGYavtDX p5T4mlKslfAQ2OrQF1vBCqPESxvWv6+GuCSYFZ2GhLolvBgP10VEn8iW7GC0DauZXBpWPHiNum5Oq ubzfH9Qy+ieAfVf1uwdgXItWQp4WbRTl+yqR5JHiqSah1mnvyY3h+Qr0OYrOxSvb2R/8XiHzMoAhT oaszNtUiL/YlmAlGoCnA==; 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Thu, 01 Jun 2023 06:02:42 +0100 Date: Thu, 01 Jun 2023 06:02:41 +0100 Message-ID: <87mt1jkc5q.wl-maz@kernel.org> From: Marc Zyngier To: Reiji Watanabe Cc: Oliver Upton , kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Will Deacon Subject: Re: [PATCH 0/4] KVM: arm64: PMU: Fix PMUVer handling on heterogeneous PMU systems In-Reply-To: <20230530125324.ijrwrvoll2detpus@google.com> References: <20230527040236.1875860-1-reijiw@google.com> <87zg5njlyn.wl-maz@kernel.org> <20230530125324.ijrwrvoll2detpus@google.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.252.176.218 X-SA-Exim-Rcpt-To: reijiw@google.com, oliver.upton@linux.dev, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, alexandru.elisei@arm.com, yuzenghui@huawei.com, suzuki.poulose@arm.com, pbonzini@redhat.com, ricarkol@google.com, jingzhangos@google.com, rananta@google.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230531_220245_737275_530BAD26 X-CRM114-Status: GOOD ( 42.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hey Reiji, On Tue, 30 May 2023 13:53:24 +0100, Reiji Watanabe wrote: > > Hi Marc, > > On Mon, May 29, 2023 at 02:39:28PM +0100, Marc Zyngier wrote: > > On Sat, 27 May 2023 05:02:32 +0100, > > Reiji Watanabe wrote: > > > > > > This series fixes issues with PMUVer handling for a guest with > > > PMU configured on heterogeneous PMU systems. > > > Specifically, it addresses the following two issues. > > > > > > [A] The default value of ID_AA64DFR0_EL1.PMUVer of the vCPU is set > > > to its sanitized value. This could be inappropriate on > > > heterogeneous PMU systems, as arm64_ftr_bits for PMUVer is defined > > > as FTR_EXACT with safe_val == 0 (when ID_AA64DFR0_EL1.PMUVer of all > > > PEs on the host is not uniform, the sanitized value will be 0). > > > > Why is this a problem? The CPUs don't implement the same version of > > the architecture, we don't get a PMU. Why should we try to do anything > > better? I really don't think we should go out or out way and make the > > code more complicated for something that doesn't really exist. > > Even when the CPUs don't implement the same version of the architecture, > if one of them implement PMUv3, KVM advertises KVM_CAP_ARM_PMU_V3, > and allows userspace to configure PMU (KVM_ARM_VCPU_PMU_V3) for vCPUs. Ah, I see it now. The kernel will register the PMU even if it decides that advertising it is wrong, and then we pick it up. Great :-/. > In this case, although KVM provides PMU emulations for the guest, > the guest's ID_AA64DFR0_EL1.PMUVer will be zero. Also, > KVM_SET_ONE_REG for ID_AA64DFR0_EL1 will never work for vCPUs > with PMU configured on such systems (since KVM also doesn't allow > userspace to set the PMUVer to 0 for the vCPUs with PMU configured). > > I would think either ID_AA64DFR0_EL1.PMUVer for the guest should > indicate PMUv3, or KVM should not allow userspace to configure PMU, > in this case. My vote is on the latter. Even if a PMU is available, we should rely on the feature exposed by the kernel to decide whether exposing a PMU or not. To be honest, this will affect almost nobody (I only know of a single one, an obscure ARMv8.0+ARMv8.2 system which is very unlikely to ever use KVM). I'm happy to take the responsibility to actively break those. > This series is a fix for the former, mainly to keep the current > behavior of KVM_CAP_ARM_PMU_V3 and KVM_ARM_VCPU_PMU_V3 on such > systems, since I wasn't sure if such systems don't really exist :) > (Also, I plan to implement a similar fix for PMCR_EL0.N on top of > those changes) > > I could make a fix for the latter instead though. What do you think ? I think this would be valuable. Also, didn't you have patches for the EL0 side of the PMU? I've been trying to look for a new version, but couldn't find it... Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel