v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks and the already merged patches obviously dropped. Jani Nikula (13): drm/dp: add DP 2.0 UHBR link rate and bw code conversions drm/dp: use more of the extended receiver cap drm/dp: add LTTPR DP 2.0 DPCD addresses drm/dp: add helper for extracting adjust 128b/132b TX FFE preset drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode drm/i915/dp: add helper for checking for UHBR link rate drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates drm/i915/dp: select 128b/132b channel encoding for UHBR rates drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 drm/i915/dp: add HAS_DP20 macro drm/i915/dg2: use 128b/132b transcoder DDI mode drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b drm/i915/dg2: update link training for 128b/132b drivers/gpu/drm/drm_dp_helper.c | 42 +++++++- drivers/gpu/drm/i915/display/intel_ddi.c | 61 +++++++++--- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + .../drm/i915/display/intel_dp_link_training.c | 99 +++++++++++++------ drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 +- include/drm/drm_dp_helper.h | 6 ++ 9 files changed, 180 insertions(+), 49 deletions(-) -- 2.30.2
v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks and the already merged patches obviously dropped. Jani Nikula (13): drm/dp: add DP 2.0 UHBR link rate and bw code conversions drm/dp: use more of the extended receiver cap drm/dp: add LTTPR DP 2.0 DPCD addresses drm/dp: add helper for extracting adjust 128b/132b TX FFE preset drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode drm/i915/dp: add helper for checking for UHBR link rate drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates drm/i915/dp: select 128b/132b channel encoding for UHBR rates drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 drm/i915/dp: add HAS_DP20 macro drm/i915/dg2: use 128b/132b transcoder DDI mode drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b drm/i915/dg2: update link training for 128b/132b drivers/gpu/drm/drm_dp_helper.c | 42 +++++++- drivers/gpu/drm/i915/display/intel_ddi.c | 61 +++++++++--- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + .../drm/i915/display/intel_dp_link_training.c | 99 +++++++++++++------ drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 +- include/drm/drm_dp_helper.h | 6 ++ 9 files changed, 180 insertions(+), 49 deletions(-) -- 2.30.2
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link rates. Handle DP 2.0 UHBR rates as special cases, though this is not pretty. Cc: dri-devel@lists.freedesktop.org Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 6d0f2c447f3b..9b2a2961fca8 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -207,15 +207,33 @@ EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); u8 drm_dp_link_rate_to_bw_code(int link_rate) { - /* Spec says link_bw = link_rate / 0.27Gbps */ - return link_rate / 27000; + switch (link_rate) { + case 1000000: + return DP_LINK_BW_10; + case 1350000: + return DP_LINK_BW_13_5; + case 2000000: + return DP_LINK_BW_20; + default: + /* Spec says link_bw = link_rate / 0.27Gbps */ + return link_rate / 27000; + } } EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); int drm_dp_bw_code_to_link_rate(u8 link_bw) { - /* Spec says link_rate = link_bw * 0.27Gbps */ - return link_bw * 27000; + switch (link_bw) { + case DP_LINK_BW_10: + return 1000000; + case DP_LINK_BW_13_5: + return 1350000; + case DP_LINK_BW_20: + return 2000000; + default: + /* Spec says link_rate = link_bw * 0.27Gbps */ + return link_bw * 27000; + } } EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); -- 2.30.2
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link rates. Handle DP 2.0 UHBR rates as special cases, though this is not pretty. Cc: dri-devel@lists.freedesktop.org Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 6d0f2c447f3b..9b2a2961fca8 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -207,15 +207,33 @@ EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); u8 drm_dp_link_rate_to_bw_code(int link_rate) { - /* Spec says link_bw = link_rate / 0.27Gbps */ - return link_rate / 27000; + switch (link_rate) { + case 1000000: + return DP_LINK_BW_10; + case 1350000: + return DP_LINK_BW_13_5; + case 2000000: + return DP_LINK_BW_20; + default: + /* Spec says link_bw = link_rate / 0.27Gbps */ + return link_rate / 27000; + } } EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); int drm_dp_bw_code_to_link_rate(u8 link_bw) { - /* Spec says link_rate = link_bw * 0.27Gbps */ - return link_bw * 27000; + switch (link_bw) { + case DP_LINK_BW_10: + return 1000000; + case DP_LINK_BW_13_5: + return 1350000; + case DP_LINK_BW_20: + return 2000000; + default: + /* Spec says link_rate = link_bw * 0.27Gbps */ + return link_bw * 27000; + } } EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); -- 2.30.2
Extend the use of extended receiver cap at 0x2200 to cover MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides the DP 2.0 128b/132b channel encoding cap. v2: Extend to DP_RECEIVER_CAP_SIZE (Ville) Cc: Lyude Paul <lyude@redhat.com> Cc: dri-devel@lists.freedesktop.org Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 9b2a2961fca8..2e74b02ed96b 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) { - u8 dpcd_ext[6]; + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; int ret; /* -- 2.30.2
Extend the use of extended receiver cap at 0x2200 to cover MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides the DP 2.0 128b/132b channel encoding cap. v2: Extend to DP_RECEIVER_CAP_SIZE (Ville) Cc: Lyude Paul <lyude@redhat.com> Cc: dri-devel@lists.freedesktop.org Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 9b2a2961fca8..2e74b02ed96b 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, u8 dpcd[DP_RECEIVER_CAP_SIZE]) { - u8 dpcd_ext[6]; + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; int ret; /* -- 2.30.2
DP 2.0 brings some new DPCD addresses for PHY repeaters. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- include/drm/drm_dp_helper.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..f3a61341011d 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1319,6 +1319,10 @@ struct drm_panel; #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ enum drm_dp_phy { DP_PHY_DPRX, -- 2.30.2
DP 2.0 brings some new DPCD addresses for PHY repeaters. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- include/drm/drm_dp_helper.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1d5b3dbb6e56..f3a61341011d 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1319,6 +1319,10 @@ struct drm_panel; #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ enum drm_dp_phy { DP_PHY_DPRX, -- 2.30.2
The DP 2.0 128b/132b channel coding uses TX FFE presets instead of vswing and pre-emphasis. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++++++++ include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 2e74b02ed96b..4d0d1e8e51fa 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -130,6 +130,20 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI } EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); +/* DP 2.0 128b/132b */ +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); + int s = ((lane & 1) ? + DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : + DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); + u8 l = dp_link_status(link_status, i); + + return (l >> s) & 0xf; +} +EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); + u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], unsigned int lane) { diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index f3a61341011d..3ee0b3ffb8a5 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1494,6 +1494,8 @@ u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], int lane); u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], int lane); +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane); u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], unsigned int lane); -- 2.30.2
The DP 2.0 128b/132b channel coding uses TX FFE presets instead of vswing and pre-emphasis. Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 14 ++++++++++++++ include/drm/drm_dp_helper.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 2e74b02ed96b..4d0d1e8e51fa 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -130,6 +130,20 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI } EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); +/* DP 2.0 128b/132b */ +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); + int s = ((lane & 1) ? + DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : + DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); + u8 l = dp_link_status(link_status, i); + + return (l >> s) & 0xf; +} +EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); + u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], unsigned int lane) { diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index f3a61341011d..3ee0b3ffb8a5 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1494,6 +1494,8 @@ u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], int lane); u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], int lane); +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane); u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], unsigned int lane); -- 2.30.2
Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register conflicts with FDI. Since we have to deal with both meanings in the same code, for different platforms, clarify the macro name so we don't forget. Bspec: 50493 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 23ef291f7b30..2361f48537b5 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -489,7 +489,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, if (crtc_state->hdmi_high_tmds_clock_ratio) temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { - temp |= TRANS_DDI_MODE_SELECT_FDI; + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; temp |= (crtc_state->fdi_lanes - 1) << 1; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { temp |= TRANS_DDI_MODE_SELECT_DP_MST; @@ -679,7 +679,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) ret = false; break; - case TRANS_DDI_MODE_SELECT_FDI: + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: ret = type == DRM_MODE_CONNECTOR_VGA; break; @@ -3558,7 +3558,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); pipe_config->lane_count = 4; break; - case TRANS_DDI_MODE_SELECT_FDI: + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); break; case TRANS_DDI_MODE_SELECT_DP_SST: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c2853cc005ee..03a94389c514 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10202,7 +10202,7 @@ enum skl_power_gate { #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) -#define TRANS_DDI_MODE_SELECT_FDI (4 << 24) +#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) #define TRANS_DDI_BPC_MASK (7 << 20) #define TRANS_DDI_BPC_8 (0 << 20) #define TRANS_DDI_BPC_10 (1 << 20) -- 2.30.2
Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register conflicts with FDI. Since we have to deal with both meanings in the same code, for different platforms, clarify the macro name so we don't forget. Bspec: 50493 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 23ef291f7b30..2361f48537b5 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -489,7 +489,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, if (crtc_state->hdmi_high_tmds_clock_ratio) temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { - temp |= TRANS_DDI_MODE_SELECT_FDI; + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; temp |= (crtc_state->fdi_lanes - 1) << 1; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { temp |= TRANS_DDI_MODE_SELECT_DP_MST; @@ -679,7 +679,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) ret = false; break; - case TRANS_DDI_MODE_SELECT_FDI: + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: ret = type == DRM_MODE_CONNECTOR_VGA; break; @@ -3558,7 +3558,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); pipe_config->lane_count = 4; break; - case TRANS_DDI_MODE_SELECT_FDI: + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); break; case TRANS_DDI_MODE_SELECT_DP_SST: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c2853cc005ee..03a94389c514 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10202,7 +10202,7 @@ enum skl_power_gate { #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) -#define TRANS_DDI_MODE_SELECT_FDI (4 << 24) +#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) #define TRANS_DDI_BPC_MASK (7 << 20) #define TRANS_DDI_BPC_8 (0 << 20) #define TRANS_DDI_BPC_10 (1 << 20) -- 2.30.2
Helpful abstraction to avoid duplication. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d28bd8c4a8a5..d189d95e4450 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -115,6 +115,12 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static void intel_dp_unset_edid(struct intel_dp *intel_dp); static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +/* Is link rate UHBR and thus 128b/132b? */ +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->port_clock >= 1000000; +} + /* update sink rates from dpcd */ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index a28fff286c21..94b568704b22 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -58,6 +58,7 @@ int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); bool intel_dp_is_edp(struct intel_dp *intel_dp); +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd); -- 2.30.2
Helpful abstraction to avoid duplication. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d28bd8c4a8a5..d189d95e4450 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -115,6 +115,12 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static void intel_dp_unset_edid(struct intel_dp *intel_dp); static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +/* Is link rate UHBR and thus 128b/132b? */ +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->port_clock >= 1000000; +} + /* update sink rates from dpcd */ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index a28fff286c21..94b568704b22 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -58,6 +58,7 @@ int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); bool intel_dp_is_edp(struct intel_dp *intel_dp); +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd); -- 2.30.2
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b TPS2 for channel equalization. v2: Use intel_dp_is_uhbr Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 508a514c5e37..36b35239da83 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -602,9 +602,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, } /* - * Pick training pattern for channel equalization. Training pattern 4 for HBR3 - * or for 1.4 devices that support it, training Pattern 3 for HBR2 - * or 1.2 devices that support it, Training Pattern 2 otherwise. + * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 + * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or + * 1.2 devices that support it, TPS2 otherwise. */ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, @@ -612,6 +612,10 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, { bool source_tps3, sink_tps3, source_tps4, sink_tps4; + /* UHBR+ use separate 128b/132b TPS2 */ + if (intel_dp_is_uhbr(crtc_state)) + return DP_TRAINING_PATTERN_2; + /* * Intel platforms that support HBR3 also support TPS4. It is mandatory * for all downstream devices that support HBR3. There are no known eDP -- 2.30.2
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b TPS2 for channel equalization. v2: Use intel_dp_is_uhbr Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 508a514c5e37..36b35239da83 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -602,9 +602,9 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, } /* - * Pick training pattern for channel equalization. Training pattern 4 for HBR3 - * or for 1.4 devices that support it, training Pattern 3 for HBR2 - * or 1.2 devices that support it, Training Pattern 2 otherwise. + * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 + * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or + * 1.2 devices that support it, TPS2 otherwise. */ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, @@ -612,6 +612,10 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, { bool source_tps3, sink_tps3, source_tps4, sink_tps4; + /* UHBR+ use separate 128b/132b TPS2 */ + if (intel_dp_is_uhbr(crtc_state)) + return DP_TRAINING_PATTERN_2; + /* * Intel platforms that support HBR3 also support TPS4. It is mandatory * for all downstream devices that support HBR3. There are no known eDP -- 2.30.2
UHBR rates and 128b/132b channel encoding go hand in hand. v2: Fix check for >= UHBR rates using intel_dp_is_uhbr() (Ville) Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 36b35239da83..4f116cd32846 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -495,7 +495,8 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp, &rate_select, 1); link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; - link_config[1] = DP_SET_ANSI_8B10B; + link_config[1] = intel_dp_is_uhbr(crtc_state) ? + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); intel_dp->DP |= DP_PORT_EN; -- 2.30.2
UHBR rates and 128b/132b channel encoding go hand in hand. v2: Fix check for >= UHBR rates using intel_dp_is_uhbr() (Ville) Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 36b35239da83..4f116cd32846 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -495,7 +495,8 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp, &rate_select, 1); link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; - link_config[1] = DP_SET_ANSI_8B10B; + link_config[1] = intel_dp_is_uhbr(crtc_state) ? + DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); intel_dp->DP |= DP_PORT_EN; -- 2.30.2
Set the DP 2.0 128b/132b channel encoding for UHBR rates. v2: Fix UHBR port clock check, use intel_dp_is_uhbr() Bspec: 54128 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 2361f48537b5..a7b7e4fafcb3 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -408,6 +408,20 @@ static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) return master_transcoder + 1; } +static void +intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 val = 0; + + if (intel_dp_is_uhbr(crtc_state)) + val = TRANS_DP2_128B132B_CHANNEL_CODING; + + intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); +} + /* * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. * @@ -2376,7 +2390,8 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_ddi_enable_pipe_clock(encoder, crtc_state); - /* 5.b Not relevant to i915 for now */ + /* 5.b Configure transcoder for DP 2.0 128b/132b */ + intel_ddi_config_transcoder_dp2(encoder, crtc_state); /* * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST -- 2.30.2
Set the DP 2.0 128b/132b channel encoding for UHBR rates. v2: Fix UHBR port clock check, use intel_dp_is_uhbr() Bspec: 54128 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 2361f48537b5..a7b7e4fafcb3 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -408,6 +408,20 @@ static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) return master_transcoder + 1; } +static void +intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 val = 0; + + if (intel_dp_is_uhbr(crtc_state)) + val = TRANS_DP2_128B132B_CHANNEL_CODING; + + intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); +} + /* * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. * @@ -2376,7 +2390,8 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_ddi_enable_pipe_clock(encoder, crtc_state); - /* 5.b Not relevant to i915 for now */ + /* 5.b Configure transcoder for DP 2.0 128b/132b */ + intel_ddi_config_transcoder_dp2(encoder, crtc_state); /* * 5.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST -- 2.30.2
Let's abstract the DP 2.0 feature. Initially just DG2. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 37c1ca266bcd..14416bd789b6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1641,6 +1641,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) +#define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) -- 2.30.2
Let's abstract the DP 2.0 feature. Initially just DG2. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 37c1ca266bcd..14416bd789b6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1641,6 +1641,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) +#define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) -- 2.30.2
128b/132b has a separate transcoder DDI mode, which also requires the MST transport select to be set. Note that we'll use DP MST also for single-stream 128b/132b. Having the FDI and 128b/132b modes share the register mode value complicates things a bit. v2: - Use HAS_DP20 abstraction for 128b/132b mode (Ville) - Use intel_dp_is_uhbr() helper Bspec: 50493 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++------ 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a7b7e4fafcb3..d2b96b2efdfe 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -506,7 +506,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; temp |= (crtc_state->fdi_lanes - 1) << 1; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { - temp |= TRANS_DDI_MODE_SELECT_DP_MST; + if (intel_dp_is_uhbr(crtc_state)) + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; + else + temp |= TRANS_DDI_MODE_SELECT_DP_MST; temp |= DDI_PORT_WIDTH(crtc_state->lane_count); if (DISPLAY_VER(dev_priv) >= 12) { @@ -694,7 +697,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) break; case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: - ret = type == DRM_MODE_CONNECTOR_VGA; + if (HAS_DP20(dev_priv)) + /* 128b/132b */ + ret = false; + else + /* FDI */ + ret = type == DRM_MODE_CONNECTOR_VGA; break; default: @@ -781,8 +789,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if ((tmp & port_mask) != ddi_select) continue; - if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == - TRANS_DDI_MODE_SELECT_DP_MST) + if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || + (HAS_DP20(dev_priv) && + (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) mst_pipe_mask |= BIT(p); *pipe_mask |= BIT(p); @@ -3573,9 +3582,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); pipe_config->lane_count = 4; break; - case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: - pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); - break; case TRANS_DDI_MODE_SELECT_DP_SST: if (encoder->type == INTEL_OUTPUT_EDP) pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); @@ -3604,6 +3610,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->infoframes.enable |= intel_hdmi_infoframes_enabled(encoder, pipe_config); break; + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: + if (!HAS_DP20(dev_priv)) { + /* FDI */ + pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); + break; + } + fallthrough; /* 128b/132b */ case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); pipe_config->lane_count = -- 2.30.2
128b/132b has a separate transcoder DDI mode, which also requires the MST transport select to be set. Note that we'll use DP MST also for single-stream 128b/132b. Having the FDI and 128b/132b modes share the register mode value complicates things a bit. v2: - Use HAS_DP20 abstraction for 128b/132b mode (Ville) - Use intel_dp_is_uhbr() helper Bspec: 50493 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++------ 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a7b7e4fafcb3..d2b96b2efdfe 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -506,7 +506,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; temp |= (crtc_state->fdi_lanes - 1) << 1; } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { - temp |= TRANS_DDI_MODE_SELECT_DP_MST; + if (intel_dp_is_uhbr(crtc_state)) + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; + else + temp |= TRANS_DDI_MODE_SELECT_DP_MST; temp |= DDI_PORT_WIDTH(crtc_state->lane_count); if (DISPLAY_VER(dev_priv) >= 12) { @@ -694,7 +697,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) break; case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: - ret = type == DRM_MODE_CONNECTOR_VGA; + if (HAS_DP20(dev_priv)) + /* 128b/132b */ + ret = false; + else + /* FDI */ + ret = type == DRM_MODE_CONNECTOR_VGA; break; default: @@ -781,8 +789,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if ((tmp & port_mask) != ddi_select) continue; - if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == - TRANS_DDI_MODE_SELECT_DP_MST) + if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || + (HAS_DP20(dev_priv) && + (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) mst_pipe_mask |= BIT(p); *pipe_mask |= BIT(p); @@ -3573,9 +3582,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); pipe_config->lane_count = 4; break; - case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: - pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); - break; case TRANS_DDI_MODE_SELECT_DP_SST: if (encoder->type == INTEL_OUTPUT_EDP) pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); @@ -3604,6 +3610,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->infoframes.enable |= intel_hdmi_infoframes_enabled(encoder, pipe_config); break; + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: + if (!HAS_DP20(dev_priv)) { + /* FDI */ + pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); + break; + } + fallthrough; /* 128b/132b */ case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); pipe_config->lane_count = -- 2.30.2
There's a new register pair for 128b/132b mode where you need to set the pixel clock in Hz. v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper Bspec: 54128 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d104441344c0..97af19fd9780 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, clear_act_sent(encoder, pipe_config); + if (intel_dp_is_uhbr(pipe_config)) { + const struct drm_display_mode *adjusted_mode = + &pipe_config->hw.adjusted_mode; + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); + + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); + } + intel_ddi_enable_transcoder_func(encoder, pipe_config); intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, -- 2.30.2
There's a new register pair for 128b/132b mode where you need to set the pixel clock in Hz. v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper Bspec: 54128 Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d104441344c0..97af19fd9780 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, clear_act_sent(encoder, pipe_config); + if (intel_dp_is_uhbr(pipe_config)) { + const struct drm_display_mode *adjusted_mode = + &pipe_config->hw.adjusted_mode; + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); + + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); + } + intel_ddi_enable_transcoder_func(encoder, pipe_config); intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, -- 2.30.2
The 128b/132b channel coding link training uses more straightforward TX FFE preset values. v2: Fix UHBR rate checks, use intel_dp_is_uhbr() helper Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++- .../drm/i915/display/intel_dp_link_training.c | 86 +++++++++++++------ 2 files changed, 70 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d2b96b2efdfe..5805bdd6e1f2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1398,11 +1398,16 @@ static int translate_signal_level(struct intel_dp *intel_dp, static int intel_ddi_dp_level(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { - u8 train_set = intel_dp->train_set[0]; - u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | - DP_TRAIN_PRE_EMPHASIS_MASK); + if (intel_dp_is_uhbr(crtc_state)) { + /* FIXME: We'll want independent presets for each lane. */ + return intel_dp->train_set[0] & DP_TX_FFE_PRESET_VALUE_MASK; + } else { + u8 train_set = intel_dp->train_set[0]; + u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | + DP_TRAIN_PRE_EMPHASIS_MASK); - return translate_signal_level(intel_dp, signal_levels); + return translate_signal_level(intel_dp, signal_levels); + } } static void diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 4f116cd32846..c10f165d1aa2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -301,6 +301,24 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, return preemph_max; } +static void intel_dp_128b132b_adjust_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + const u8 link_status[DP_LINK_STATUS_SIZE]) +{ + int lane; + u8 tx_ffe = 0; + + /* + * FIXME: We'll want independent presets for each lane. See also + * intel_ddi_dp_level() and intel_snps_phy_ddi_vswing_sequence(). + */ + for (lane = 0; lane < crtc_state->lane_count; lane++) + tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); + + for (lane = 0; lane < crtc_state->lane_count; lane++) + intel_dp->train_set[lane] = tx_ffe; +} + void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, @@ -313,6 +331,11 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp, u8 voltage_max; u8 preemph_max; + if (intel_dp_is_uhbr(crtc_state)) { + intel_dp_128b132b_adjust_train(intel_dp, crtc_state, link_status); + return; + } + for (lane = 0; lane < crtc_state->lane_count; lane++) { v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); @@ -402,14 +425,21 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp, u8 train_set = intel_dp->train_set[0]; char phy_name[10]; - drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", - train_set & DP_TRAIN_VOLTAGE_SWING_MASK, - train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> - DP_TRAIN_PRE_EMPHASIS_SHIFT, - train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? - " (max)" : "", - intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); + if (intel_dp_is_uhbr(crtc_state)) { + /* FIXME: We'll want independent presets for each lane. */ + drm_dbg_kms(&dev_priv->drm, "%s: Using 128b/132b TX FFE preset %u\n", + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), + train_set & DP_TX_FFE_PRESET_VALUE_MASK); + } else { + drm_dbg_kms(&dev_priv->drm, "%s: Using 8b/10b vswing level %d%s, pre-emphasis level %d%s\n", + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), + train_set & DP_TRAIN_VOLTAGE_SWING_MASK, + train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", + (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT, + train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? + " (max)" : ""); + } if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) intel_dp->set_signal_levels(intel_dp, crtc_state); @@ -565,18 +595,21 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, return true; } - if (voltage_tries == 5) { - drm_dbg_kms(&i915->drm, - "Same voltage tried 5 times\n"); - return false; - } + /* FIXME: 128b/132b needs better abstractions here. */ + if (!intel_dp_is_uhbr(crtc_state)) { + if (voltage_tries == 5) { + drm_dbg_kms(&i915->drm, + "Same voltage tried 5 times\n"); + return false; + } - if (max_vswing_reached) { - drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); - return false; - } + if (max_vswing_reached) { + drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); + return false; + } - voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; + voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; + } /* Update training set as requested by target */ intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, @@ -587,14 +620,17 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, return false; } - if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == - voltage) - ++voltage_tries; - else - voltage_tries = 1; + /* FIXME: 128b/132b needs better abstractions here. */ + if (!intel_dp_is_uhbr(crtc_state)) { + if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == + voltage) + ++voltage_tries; + else + voltage_tries = 1; - if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) - max_vswing_reached = true; + if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) + max_vswing_reached = true; + } } drm_err(&i915->drm, -- 2.30.2
The 128b/132b channel coding link training uses more straightforward TX FFE preset values. v2: Fix UHBR rate checks, use intel_dp_is_uhbr() helper Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++- .../drm/i915/display/intel_dp_link_training.c | 86 +++++++++++++------ 2 files changed, 70 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d2b96b2efdfe..5805bdd6e1f2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1398,11 +1398,16 @@ static int translate_signal_level(struct intel_dp *intel_dp, static int intel_ddi_dp_level(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { - u8 train_set = intel_dp->train_set[0]; - u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | - DP_TRAIN_PRE_EMPHASIS_MASK); + if (intel_dp_is_uhbr(crtc_state)) { + /* FIXME: We'll want independent presets for each lane. */ + return intel_dp->train_set[0] & DP_TX_FFE_PRESET_VALUE_MASK; + } else { + u8 train_set = intel_dp->train_set[0]; + u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | + DP_TRAIN_PRE_EMPHASIS_MASK); - return translate_signal_level(intel_dp, signal_levels); + return translate_signal_level(intel_dp, signal_levels); + } } static void diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 4f116cd32846..c10f165d1aa2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -301,6 +301,24 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, return preemph_max; } +static void intel_dp_128b132b_adjust_train(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + const u8 link_status[DP_LINK_STATUS_SIZE]) +{ + int lane; + u8 tx_ffe = 0; + + /* + * FIXME: We'll want independent presets for each lane. See also + * intel_ddi_dp_level() and intel_snps_phy_ddi_vswing_sequence(). + */ + for (lane = 0; lane < crtc_state->lane_count; lane++) + tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); + + for (lane = 0; lane < crtc_state->lane_count; lane++) + intel_dp->train_set[lane] = tx_ffe; +} + void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, @@ -313,6 +331,11 @@ intel_dp_get_adjust_train(struct intel_dp *intel_dp, u8 voltage_max; u8 preemph_max; + if (intel_dp_is_uhbr(crtc_state)) { + intel_dp_128b132b_adjust_train(intel_dp, crtc_state, link_status); + return; + } + for (lane = 0; lane < crtc_state->lane_count; lane++) { v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); @@ -402,14 +425,21 @@ void intel_dp_set_signal_levels(struct intel_dp *intel_dp, u8 train_set = intel_dp->train_set[0]; char phy_name[10]; - drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", - train_set & DP_TRAIN_VOLTAGE_SWING_MASK, - train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> - DP_TRAIN_PRE_EMPHASIS_SHIFT, - train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? - " (max)" : "", - intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); + if (intel_dp_is_uhbr(crtc_state)) { + /* FIXME: We'll want independent presets for each lane. */ + drm_dbg_kms(&dev_priv->drm, "%s: Using 128b/132b TX FFE preset %u\n", + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), + train_set & DP_TX_FFE_PRESET_VALUE_MASK); + } else { + drm_dbg_kms(&dev_priv->drm, "%s: Using 8b/10b vswing level %d%s, pre-emphasis level %d%s\n", + intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), + train_set & DP_TRAIN_VOLTAGE_SWING_MASK, + train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", + (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT, + train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? + " (max)" : ""); + } if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) intel_dp->set_signal_levels(intel_dp, crtc_state); @@ -565,18 +595,21 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, return true; } - if (voltage_tries == 5) { - drm_dbg_kms(&i915->drm, - "Same voltage tried 5 times\n"); - return false; - } + /* FIXME: 128b/132b needs better abstractions here. */ + if (!intel_dp_is_uhbr(crtc_state)) { + if (voltage_tries == 5) { + drm_dbg_kms(&i915->drm, + "Same voltage tried 5 times\n"); + return false; + } - if (max_vswing_reached) { - drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); - return false; - } + if (max_vswing_reached) { + drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); + return false; + } - voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; + voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; + } /* Update training set as requested by target */ intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, @@ -587,14 +620,17 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, return false; } - if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == - voltage) - ++voltage_tries; - else - voltage_tries = 1; + /* FIXME: 128b/132b needs better abstractions here. */ + if (!intel_dp_is_uhbr(crtc_state)) { + if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == + voltage) + ++voltage_tries; + else + voltage_tries = 1; - if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) - max_vswing_reached = true; + if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) + max_vswing_reached = true; + } } drm_err(&i915->drm, -- 2.30.2
== Series Details == Series: drm/i915/dp: dp 2.0 enabling prep work (rev3) URL : https://patchwork.freedesktop.org/series/93800/ State : warning == Summary == $ dim checkpatch origin/drm-tip a3665dc8b3d2 drm/dp: add DP 2.0 UHBR link rate and bw code conversions 68ec9d98ee90 drm/dp: use more of the extended receiver cap 48940950af3c drm/dp: add LTTPR DP 2.0 DPCD addresses a2c94be7e9b9 drm/dp: add helper for extracting adjust 128b/132b TX FFE preset c762623aaaba drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode e99cd06140c4 drm/i915/dp: add helper for checking for UHBR link rate 9334d33d2624 drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates 13bcc2d6e808 drm/i915/dp: select 128b/132b channel encoding for UHBR rates 1fc3c6d399c1 drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 23ec558b7af4 drm/i915/dp: add HAS_DP20 macro fcf2455de71f drm/i915/dg2: use 128b/132b transcoder DDI mode 5a7810bd5e6f drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b c586238887e7 drm/i915/dg2: update link training for 128b/132b -:27: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return #27: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1404: + return intel_dp->train_set[0] & DP_TX_FFE_PRESET_VALUE_MASK; + } else { total: 0 errors, 1 warnings, 0 checks, 139 lines checked
== Series Details == Series: drm/i915/dp: dp 2.0 enabling prep work (rev3) URL : https://patchwork.freedesktop.org/series/93800/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: error: incompatible types in comparison expression (different type sizes): +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: unsigned long * +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:354:16: unsigned long long * +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4483:31: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4485:33: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:294:25: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:294:25: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:294:25: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:344:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:344:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:344:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c:117:1: warning: no newline at end of file +drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:123:51: error: marked inline, but without a definition +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2p
[-- Attachment #1: Type: text/plain, Size: 4095 bytes --] == Series Details == Series: drm/i915/dp: dp 2.0 enabling prep work (rev3) URL : https://patchwork.freedesktop.org/series/93800/ State : success == Summary == CI Bug Log - changes from CI_DRM_10565 -> Patchwork_21002 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/index.html Known issues ------------ Here are the changes found in Patchwork_21002 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html * igt@core_hotunplug@unbind-rebind: - fi-bdw-5557u: NOTRUN -> [WARN][2] ([i915#3718]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#2868]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html #### Possible fixes #### * igt@i915_selftest@live@gt_pm: - {fi-jsl-1}: [DMESG-FAIL][6] ([i915#1886]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/fi-jsl-1/igt@i915_selftest@live@gt_pm.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/fi-jsl-1/igt@i915_selftest@live@gt_pm.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718 Participating hosts (47 -> 39) ------------------------------ Missing (8): fi-ilk-m540 bat-adls-5 bat-dg1-6 fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus bat-jsl-1 Build changes ------------- * Linux: CI_DRM_10565 -> Patchwork_21002 CI-20190529: 20190529 CI_DRM_10565: 8c3cd60dcfa81a649b14f0705eb5e5c9336f1881 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6201: be0d02ff0775235ead63ccb1e3a1e8c10f0209cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21002: c586238887e774ccaf7b7d0dc0e690696c6e410d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c586238887e7 drm/i915/dg2: update link training for 128b/132b 5a7810bd5e6f drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b fcf2455de71f drm/i915/dg2: use 128b/132b transcoder DDI mode 23ec558b7af4 drm/i915/dp: add HAS_DP20 macro 1fc3c6d399c1 drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 13bcc2d6e808 drm/i915/dp: select 128b/132b channel encoding for UHBR rates 9334d33d2624 drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates e99cd06140c4 drm/i915/dp: add helper for checking for UHBR link rate c762623aaaba drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode a2c94be7e9b9 drm/dp: add helper for extracting adjust 128b/132b TX FFE preset 48940950af3c drm/dp: add LTTPR DP 2.0 DPCD addresses 68ec9d98ee90 drm/dp: use more of the extended receiver cap a3665dc8b3d2 drm/dp: add DP 2.0 UHBR link rate and bw code conversions == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/index.html [-- Attachment #2: Type: text/html, Size: 4882 bytes --]
I thought I remembered an issue with this but looked up the previous emails,
and it looks like that this change actually should be safe!
Signed-off-by: Lyude Paul <lyude@redhat.com>
On Thu, 2021-09-09 at 15:51 +0300, Jani Nikula wrote:
> Extend the use of extended receiver cap at 0x2200 to cover
> MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
> the DP 2.0 128b/132b channel encoding cap.
>
> v2: Extend to DP_RECEIVER_CAP_SIZE (Ville)
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index 9b2a2961fca8..2e74b02ed96b 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8
> dpcd[DP_RECEIVER_CAP_SIZE])
> static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
> u8 dpcd[DP_RECEIVER_CAP_SIZE])
> {
> - u8 dpcd_ext[6];
> + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
> int ret;
>
> /*
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
I thought I remembered an issue with this but looked up the previous emails,
and it looks like that this change actually should be safe!
Signed-off-by: Lyude Paul <lyude@redhat.com>
On Thu, 2021-09-09 at 15:51 +0300, Jani Nikula wrote:
> Extend the use of extended receiver cap at 0x2200 to cover
> MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
> the DP 2.0 128b/132b channel encoding cap.
>
> v2: Extend to DP_RECEIVER_CAP_SIZE (Ville)
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/drm_dp_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index 9b2a2961fca8..2e74b02ed96b 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8
> dpcd[DP_RECEIVER_CAP_SIZE])
> static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
> u8 dpcd[DP_RECEIVER_CAP_SIZE])
> {
> - u8 dpcd_ext[6];
> + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
> int ret;
>
> /*
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
…whoops, that was supposed to be:
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Thu, 2021-09-09 at 12:18 -0400, Lyude Paul wrote:
> I thought I remembered an issue with this but looked up the previous emails,
> and it looks like that this change actually should be safe!
>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
>
> On Thu, 2021-09-09 at 15:51 +0300, Jani Nikula wrote:
> > Extend the use of extended receiver cap at 0x2200 to cover
> > MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
> > the DP 2.0 128b/132b channel encoding cap.
> >
> > v2: Extend to DP_RECEIVER_CAP_SIZE (Ville)
> >
> > Cc: Lyude Paul <lyude@redhat.com>
> > Cc: dri-devel@lists.freedesktop.org
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > ---
> > drivers/gpu/drm/drm_dp_helper.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > b/drivers/gpu/drm/drm_dp_helper.c
> > index 9b2a2961fca8..2e74b02ed96b 100644
> > --- a/drivers/gpu/drm/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > @@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8
> > dpcd[DP_RECEIVER_CAP_SIZE])
> > static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
> > u8 dpcd[DP_RECEIVER_CAP_SIZE])
> > {
> > - u8 dpcd_ext[6];
> > + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
> > int ret;
> >
> > /*
>
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
…whoops, that was supposed to be:
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Thu, 2021-09-09 at 12:18 -0400, Lyude Paul wrote:
> I thought I remembered an issue with this but looked up the previous emails,
> and it looks like that this change actually should be safe!
>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
>
> On Thu, 2021-09-09 at 15:51 +0300, Jani Nikula wrote:
> > Extend the use of extended receiver cap at 0x2200 to cover
> > MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
> > the DP 2.0 128b/132b channel encoding cap.
> >
> > v2: Extend to DP_RECEIVER_CAP_SIZE (Ville)
> >
> > Cc: Lyude Paul <lyude@redhat.com>
> > Cc: dri-devel@lists.freedesktop.org
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > ---
> > drivers/gpu/drm/drm_dp_helper.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > b/drivers/gpu/drm/drm_dp_helper.c
> > index 9b2a2961fca8..2e74b02ed96b 100644
> > --- a/drivers/gpu/drm/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > @@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8
> > dpcd[DP_RECEIVER_CAP_SIZE])
> > static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
> > u8 dpcd[DP_RECEIVER_CAP_SIZE])
> > {
> > - u8 dpcd_ext[6];
> > + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
> > int ret;
> >
> > /*
>
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
[-- Attachment #1: Type: text/plain, Size: 30268 bytes --] == Series Details == Series: drm/i915/dp: dp 2.0 enabling prep work (rev3) URL : https://patchwork.freedesktop.org/series/93800/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10565_full -> Patchwork_21002_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_21002_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21002_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_21002_full: ### IGT changes ### #### Possible regressions #### * igt@kms_cursor_legacy@cursor-vs-flip-legacy: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-skl1/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl5/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile: - shard-iclb: [PASS][3] -> [SKIP][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes: - shard-tglb: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html Known issues ------------ Here are the changes found in Patchwork_21002_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_persistence@smoketest: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-snb5/igt@gem_ctx_persistence@smoketest.html - shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2896]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb2/igt@gem_ctx_persistence@smoketest.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb2/igt@gem_ctx_persistence@smoketest.html * igt@gem_eio@unwedge-stress: - shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / [i915#3063] / [i915#3648]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb3/igt@gem_eio@unwedge-stress.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb2/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271]) +397 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-snb6/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#118] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-glk8/igt@gem_exec_whisper@basic-contexts-forked-all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-glk2/igt@gem_exec_whisper@basic-contexts-forked-all.html * igt@gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#307]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-iclb5/igt@gem_mmap_gtt@cpuset-big-copy-odd.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb3/igt@gem_mmap_gtt@cpuset-big-copy-odd.html * igt@gem_render_copy@linear-to-vebox-y-tiled: - shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-glk7/igt@gem_render_copy@linear-to-vebox-y-tiled.html - shard-iclb: NOTRUN -> [SKIP][20] ([i915#768]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@gem_render_copy@linear-to-vebox-y-tiled.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-tglb: NOTRUN -> [SKIP][21] ([i915#3297]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb6/igt@gem_userptr_blits@dmabuf-unsync.html - shard-iclb: NOTRUN -> [SKIP][22] ([i915#3297]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][23] ([i915#3002]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl7/igt@gem_userptr_blits@input-checking.html - shard-snb: NOTRUN -> [DMESG-WARN][24] ([i915#3002]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-snb7/igt@gem_userptr_blits@input-checking.html * igt@i915_module_load@reload-no-display: - shard-iclb: [PASS][25] -> [DMESG-WARN][26] ([i915#2867]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-iclb7/igt@i915_module_load@reload-no-display.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb3/igt@i915_module_load@reload-no-display.html * igt@kms_big_fb@y-tiled-8bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][27] ([fdo#110725] / [fdo#111614]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][28] ([fdo#110723]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-addfb-size-overflow: - shard-tglb: NOTRUN -> [SKIP][29] ([fdo#111615]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb3/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][30] ([i915#3722]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl6/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +9 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl1/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-glk7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html - shard-iclb: NOTRUN -> [SKIP][34] ([fdo#109278] / [i915#3886]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][35] ([i915#3689]) +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb5/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs.html * igt@kms_chamelium@vga-hpd-fast: - shard-tglb: NOTRUN -> [SKIP][36] ([fdo#109284] / [fdo#111827]) +2 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb5/igt@kms_chamelium@vga-hpd-fast.html * igt@kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-skl3/igt@kms_color@pipe-c-ctm-0-25.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl10/igt@kms_color@pipe-c-ctm-0-25.html * igt@kms_color_chamelium@pipe-a-ctm-negative: - shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-kbl4/igt@kms_color_chamelium@pipe-a-ctm-negative.html * igt@kms_color_chamelium@pipe-b-gamma: - shard-iclb: NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@kms_color_chamelium@pipe-b-gamma.html - shard-glk: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-glk7/igt@kms_color_chamelium@pipe-b-gamma.html * igt@kms_color_chamelium@pipe-c-ctm-0-25: - shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +15 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl6/igt@kms_color_chamelium@pipe-c-ctm-0-25.html * igt@kms_color_chamelium@pipe-d-ctm-0-5: - shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl6/igt@kms_color_chamelium@pipe-d-ctm-0-5.html * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes: - shard-snb: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +15 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-snb5/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html * igt@kms_content_protection@atomic-dpms: - shard-apl: NOTRUN -> [TIMEOUT][45] ([i915#1319]) +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl7/igt@kms_content_protection@atomic-dpms.html * igt@kms_cursor_crc@pipe-a-cursor-32x10-random: - shard-tglb: NOTRUN -> [SKIP][46] ([i915#3359]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-32x10-random.html * igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement: - shard-tglb: NOTRUN -> [SKIP][47] ([i915#3319]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement.html * igt@kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][48] -> [DMESG-WARN][49] ([i915#180]) +1 similar issue [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html * igt@kms_cursor_crc@pipe-d-cursor-dpms: - shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109278]) +4 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@kms_cursor_crc@pipe-d-cursor-dpms.html * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic: - shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109274] / [fdo#109278]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html * igt@kms_fbcon_fbt@psr-suspend: - shard-tglb: [PASS][52] -> [INCOMPLETE][53] ([i915#2411] / [i915#456]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb2/igt@kms_fbcon_fbt@psr-suspend.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb7/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [PASS][54] -> [FAIL][55] ([i915#79]) +2 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1: - shard-glk: [PASS][56] -> [FAIL][57] ([i915#79]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [PASS][58] -> [DMESG-WARN][59] ([i915#180]) +2 similar issues [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1: - shard-skl: [PASS][60] -> [FAIL][61] ([i915#2122]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs: - shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#2672]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move: - shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109280]) +5 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite: - shard-tglb: NOTRUN -> [SKIP][64] ([fdo#111825]) +6 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt: - shard-skl: NOTRUN -> [SKIP][65] ([fdo#109271]) +48 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271]) +10 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-kbl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt: - shard-iclb: [PASS][67] -> [FAIL][68] ([i915#2546]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-iclb3/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb2/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html * igt@kms_hdr@static-toggle: - shard-tglb: NOTRUN -> [SKIP][69] ([i915#1187]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb5/igt@kms_hdr@static-toggle.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d: - shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#533]) +1 similar issue [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-apl: NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265]) +3 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][72] ([i915#265]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-kbl: NOTRUN -> [FAIL][73] ([fdo#108145] / [i915#265]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-kbl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_plane_lowres@pipe-b-tiling-x: - shard-iclb: NOTRUN -> [SKIP][74] ([i915#3536]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@kms_plane_lowres@pipe-b-tiling-x.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4: - shard-kbl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#658]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-kbl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3: - shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658]) +1 similar issue [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4: - shard-tglb: NOTRUN -> [SKIP][77] ([i915#2920]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html - shard-iclb: NOTRUN -> [SKIP][78] ([i915#658]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][79] -> [SKIP][80] ([fdo#109441]) +1 similar issue [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_writeback@writeback-fb-id: - shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2437]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl7/igt@kms_writeback@writeback-fb-id.html * igt@kms_writeback@writeback-invalid-parameters: - shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2437]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-kbl4/igt@kms_writeback@writeback-invalid-parameters.html * igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame: - shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271]) +222 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl7/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html * igt@perf@polling-parameterized: - shard-iclb: [PASS][84] -> [FAIL][85] ([i915#1542]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-iclb8/igt@perf@polling-parameterized.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb8/igt@perf@polling-parameterized.html - shard-skl: NOTRUN -> [FAIL][86] ([i915#1542]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl6/igt@perf@polling-parameterized.html * igt@perf_pmu@module-unload: - shard-iclb: [PASS][87] -> [DMESG-WARN][88] ([i915#262]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-iclb7/igt@perf_pmu@module-unload.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-iclb3/igt@perf_pmu@module-unload.html * igt@sysfs_clients@pidname: - shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994]) +2 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-apl1/igt@sysfs_clients@pidname.html * igt@sysfs_clients@split-50: - shard-skl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2994]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl6/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@fbdev@nullptr: - {shard-rkl}: [SKIP][91] ([i915#2582]) -> [PASS][92] [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-1/igt@fbdev@nullptr.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@fbdev@nullptr.html * igt@gem_eio@hibernate: - {shard-rkl}: [TIMEOUT][93] ([i915#3811]) -> [PASS][94] [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-5/igt@gem_eio@hibernate.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-1/igt@gem_eio@hibernate.html * igt@gem_eio@reset-stress: - {shard-rkl}: [FAIL][95] ([i915#3115]) -> [PASS][96] [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-2/igt@gem_eio@reset-stress.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@gem_eio@reset-stress.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [FAIL][97] ([i915#2846]) -> [PASS][98] [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-glk8/igt@gem_exec_fair@basic-deadline.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-glk2/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [SKIP][99] ([fdo#109271]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [FAIL][101] ([i915#2842]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs0.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_workarounds@suspend-resume: - shard-tglb: [INCOMPLETE][103] ([i915#456]) -> [PASS][104] [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-tglb7/igt@gem_workarounds@suspend-resume.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-tglb5/igt@gem_workarounds@suspend-resume.html * igt@i915_pm_backlight@fade_with_suspend: - {shard-rkl}: [SKIP][105] ([i915#3012]) -> [PASS][106] [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-2/igt@i915_pm_backlight@fade_with_suspend.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@i915_pm_backlight@fade_with_suspend.html * igt@kms_atomic@test-only: - {shard-rkl}: [SKIP][107] ([i915#1845]) -> [PASS][108] +26 similar issues [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-2/igt@kms_atomic@test-only.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_atomic@test-only.html * igt@kms_big_fb@linear-32bpp-rotate-0: - {shard-rkl}: [SKIP][109] ([i915#3638]) -> [PASS][110] +1 similar issue [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-2/igt@kms_big_fb@linear-32bpp-rotate-0.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_big_fb@linear-32bpp-rotate-0.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180: - {shard-rkl}: [SKIP][111] ([i915#3721]) -> [PASS][112] +5 similar issues [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html * igt@kms_color@pipe-a-ctm-0-25: - shard-skl: [DMESG-WARN][113] ([i915#1982]) -> [PASS][114] [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-skl2/igt@kms_color@pipe-a-ctm-0-25.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl1/igt@kms_color@pipe-a-ctm-0-25.html * igt@kms_color@pipe-b-ctm-0-25: - {shard-rkl}: [SKIP][115] ([i915#1149] / [i915#1849] / [i915#4070]) -> [PASS][116] +1 similar issue [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-2/igt@kms_color@pipe-b-ctm-0-25.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_color@pipe-b-ctm-0-25.html * igt@kms_cursor_crc@pipe-b-cursor-256x85-random: - {shard-rkl}: [SKIP][117] ([fdo#112022] / [i915#4070]) -> [PASS][118] +8 similar issues [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - {shard-rkl}: [SKIP][119] ([fdo#111825] / [i915#4070]) -> [PASS][120] [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html * igt@kms_dp_aux_dev: - {shard-rkl}: [SKIP][121] ([i915#1257]) -> [PASS][122] [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-1/igt@kms_dp_aux_dev.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_dp_aux_dev.html * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: - {shard-rkl}: [SKIP][123] ([fdo#111314]) -> [PASS][124] +4 similar issues [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-2/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html * igt@kms_fbcon_fbt@fbc-suspend: - {shard-rkl}: [SKIP][125] ([i915#1849]) -> [PASS][126] +29 similar issues [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-2/igt@kms_fbcon_fbt@fbc-suspend.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_fbcon_fbt@psr-suspend: - {shard-rkl}: [SKIP][127] ([fdo#110189] / [i915#3955]) -> [PASS][128] [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [FAIL][129] ([i915#79]) -> [PASS][130] +1 similar issue [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1: - shard-kbl: [FAIL][131] ([i915#79]) -> [PASS][132] [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html * igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1: - shard-glk: [FAIL][133] ([i915#79]) -> [PASS][134] +2 similar issues [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1: - shard-kbl: [DMESG-WARN][135] ([i915#180]) -> [PASS][136] +2 similar issues [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html * igt@kms_mmap_write_crc@main: - {shard-rkl}: [FAIL][137] -> [PASS][138] [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-6/igt@kms_mmap_write_crc@main.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_mmap_write_crc@main.html * igt@kms_plane@plane-panning-top-left@pipe-b-planes: - {shard-rkl}: [SKIP][139] ([i915#3558]) -> [PASS][140] +1 similar issue [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-rkl-2/igt@kms_plane@plane-panning-top-left@pipe-b-planes.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/shard-rkl-6/igt@kms_plane@plane-panning-top-left@pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][141] ([fdo#108145] / [i915#265]) -> [PASS][142] [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10565/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21002/index.html [-- Attachment #2: Type: text/html, Size: 33458 bytes --]
On Thu, Sep 09, 2021 at 03:51:53PM +0300, Jani Nikula wrote: > The bw code equals link_rate / 0.27 Gbps only for 8b/10b link > rates. Handle DP 2.0 UHBR rates as special cases, though this is not > pretty. > > Cc: dri-devel@lists.freedesktop.org > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/drm_dp_helper.c | 26 ++++++++++++++++++++++---- > 1 file changed, 22 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index 6d0f2c447f3b..9b2a2961fca8 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -207,15 +207,33 @@ EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); > > u8 drm_dp_link_rate_to_bw_code(int link_rate) > { > - /* Spec says link_bw = link_rate / 0.27Gbps */ > - return link_rate / 27000; > + switch (link_rate) { > + case 1000000: > + return DP_LINK_BW_10; > + case 1350000: > + return DP_LINK_BW_13_5; > + case 2000000: > + return DP_LINK_BW_20; > + default: > + /* Spec says link_bw = link_rate / 0.27Gbps */ > + return link_rate / 27000; > + } > } > EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); > > int drm_dp_bw_code_to_link_rate(u8 link_bw) > { > - /* Spec says link_rate = link_bw * 0.27Gbps */ > - return link_bw * 27000; > + switch (link_bw) { > + case DP_LINK_BW_10: > + return 1000000; > + case DP_LINK_BW_13_5: > + return 1350000; > + case DP_LINK_BW_20: > + return 2000000; > + default: > + /* Spec says link_rate = link_bw * 0.27Gbps */ > + return link_bw * 27000; > + } > } > EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); > > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, Sep 09, 2021 at 03:51:53PM +0300, Jani Nikula wrote: > The bw code equals link_rate / 0.27 Gbps only for 8b/10b link > rates. Handle DP 2.0 UHBR rates as special cases, though this is not > pretty. > > Cc: dri-devel@lists.freedesktop.org > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/drm_dp_helper.c | 26 ++++++++++++++++++++++---- > 1 file changed, 22 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index 6d0f2c447f3b..9b2a2961fca8 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -207,15 +207,33 @@ EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); > > u8 drm_dp_link_rate_to_bw_code(int link_rate) > { > - /* Spec says link_bw = link_rate / 0.27Gbps */ > - return link_rate / 27000; > + switch (link_rate) { > + case 1000000: > + return DP_LINK_BW_10; > + case 1350000: > + return DP_LINK_BW_13_5; > + case 2000000: > + return DP_LINK_BW_20; > + default: > + /* Spec says link_bw = link_rate / 0.27Gbps */ > + return link_rate / 27000; > + } > } > EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); > > int drm_dp_bw_code_to_link_rate(u8 link_bw) > { > - /* Spec says link_rate = link_bw * 0.27Gbps */ > - return link_bw * 27000; > + switch (link_bw) { > + case DP_LINK_BW_10: > + return 1000000; > + case DP_LINK_BW_13_5: > + return 1350000; > + case DP_LINK_BW_20: > + return 2000000; > + default: > + /* Spec says link_rate = link_bw * 0.27Gbps */ > + return link_bw * 27000; > + } > } > EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); > > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, Sep 09, 2021 at 03:51:58PM +0300, Jani Nikula wrote: > Helpful abstraction to avoid duplication. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index d28bd8c4a8a5..d189d95e4450 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -115,6 +115,12 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) > static void intel_dp_unset_edid(struct intel_dp *intel_dp); > static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); > > +/* Is link rate UHBR and thus 128b/132b? */ > +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) > +{ > + return crtc_state->port_clock >= 1000000; > +} > + > /* update sink rates from dpcd */ > static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) > { > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h > index a28fff286c21..94b568704b22 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -58,6 +58,7 @@ int intel_dp_compute_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config, > struct drm_connector_state *conn_state); > bool intel_dp_is_edp(struct intel_dp *intel_dp); > +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); > bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); > enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, > bool long_hpd); > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, Sep 09, 2021 at 03:51:58PM +0300, Jani Nikula wrote: > Helpful abstraction to avoid duplication. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++ > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index d28bd8c4a8a5..d189d95e4450 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -115,6 +115,12 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) > static void intel_dp_unset_edid(struct intel_dp *intel_dp); > static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); > > +/* Is link rate UHBR and thus 128b/132b? */ > +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) > +{ > + return crtc_state->port_clock >= 1000000; > +} > + > /* update sink rates from dpcd */ > static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) > { > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h > index a28fff286c21..94b568704b22 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -58,6 +58,7 @@ int intel_dp_compute_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config, > struct drm_connector_state *conn_state); > bool intel_dp_is_edp(struct intel_dp *intel_dp); > +bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); > bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); > enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, > bool long_hpd); > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, Sep 09, 2021 at 03:52:02PM +0300, Jani Nikula wrote: > Let's abstract the DP 2.0 feature. Initially just DG2. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 37c1ca266bcd..14416bd789b6 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1641,6 +1641,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) > > #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) > +#define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) > > #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) > #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, Sep 09, 2021 at 03:52:02PM +0300, Jani Nikula wrote: > Let's abstract the DP 2.0 feature. Initially just DG2. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 37c1ca266bcd..14416bd789b6 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1641,6 +1641,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) > > #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) > +#define HAS_DP20(dev_priv) (IS_DG2(dev_priv)) > > #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl) > #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, Sep 09, 2021 at 03:52:03PM +0300, Jani Nikula wrote: > 128b/132b has a separate transcoder DDI mode, which also requires the > MST transport select to be set. Note that we'll use DP MST also for > single-stream 128b/132b. > > Having the FDI and 128b/132b modes share the register mode value > complicates things a bit. > > v2: > - Use HAS_DP20 abstraction for 128b/132b mode (Ville) > - Use intel_dp_is_uhbr() helper > > Bspec: 50493 > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++------ > 1 file changed, 20 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index a7b7e4fafcb3..d2b96b2efdfe 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -506,7 +506,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, > temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; > temp |= (crtc_state->fdi_lanes - 1) << 1; > } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { > - temp |= TRANS_DDI_MODE_SELECT_DP_MST; > + if (intel_dp_is_uhbr(crtc_state)) > + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; > + else > + temp |= TRANS_DDI_MODE_SELECT_DP_MST; > temp |= DDI_PORT_WIDTH(crtc_state->lane_count); > > if (DISPLAY_VER(dev_priv) >= 12) { > @@ -694,7 +697,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) > break; > > case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: > - ret = type == DRM_MODE_CONNECTOR_VGA; > + if (HAS_DP20(dev_priv)) > + /* 128b/132b */ > + ret = false; > + else > + /* FDI */ > + ret = type == DRM_MODE_CONNECTOR_VGA; > break; > > default: > @@ -781,8 +789,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, > if ((tmp & port_mask) != ddi_select) > continue; > > - if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == > - TRANS_DDI_MODE_SELECT_DP_MST) > + if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || > + (HAS_DP20(dev_priv) && > + (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) > mst_pipe_mask |= BIT(p); > > *pipe_mask |= BIT(p); > @@ -3573,9 +3582,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, > pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); > pipe_config->lane_count = 4; > break; > - case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: > - pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); > - break; > case TRANS_DDI_MODE_SELECT_DP_SST: > if (encoder->type == INTEL_OUTPUT_EDP) > pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); > @@ -3604,6 +3610,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, > pipe_config->infoframes.enable |= > intel_hdmi_infoframes_enabled(encoder, pipe_config); > break; > + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: > + if (!HAS_DP20(dev_priv)) { > + /* FDI */ > + pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); > + break; > + } > + fallthrough; /* 128b/132b */ > case TRANS_DDI_MODE_SELECT_DP_MST: > pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); > pipe_config->lane_count = > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, Sep 09, 2021 at 03:52:03PM +0300, Jani Nikula wrote: > 128b/132b has a separate transcoder DDI mode, which also requires the > MST transport select to be set. Note that we'll use DP MST also for > single-stream 128b/132b. > > Having the FDI and 128b/132b modes share the register mode value > complicates things a bit. > > v2: > - Use HAS_DP20 abstraction for 128b/132b mode (Ville) > - Use intel_dp_is_uhbr() helper > > Bspec: 50493 > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++------ > 1 file changed, 20 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index a7b7e4fafcb3..d2b96b2efdfe 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -506,7 +506,10 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, > temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; > temp |= (crtc_state->fdi_lanes - 1) << 1; > } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { > - temp |= TRANS_DDI_MODE_SELECT_DP_MST; > + if (intel_dp_is_uhbr(crtc_state)) > + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; > + else > + temp |= TRANS_DDI_MODE_SELECT_DP_MST; > temp |= DDI_PORT_WIDTH(crtc_state->lane_count); > > if (DISPLAY_VER(dev_priv) >= 12) { > @@ -694,7 +697,12 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) > break; > > case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: > - ret = type == DRM_MODE_CONNECTOR_VGA; > + if (HAS_DP20(dev_priv)) > + /* 128b/132b */ > + ret = false; > + else > + /* FDI */ > + ret = type == DRM_MODE_CONNECTOR_VGA; > break; > > default: > @@ -781,8 +789,9 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, > if ((tmp & port_mask) != ddi_select) > continue; > > - if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == > - TRANS_DDI_MODE_SELECT_DP_MST) > + if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || > + (HAS_DP20(dev_priv) && > + (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) > mst_pipe_mask |= BIT(p); > > *pipe_mask |= BIT(p); > @@ -3573,9 +3582,6 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, > pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); > pipe_config->lane_count = 4; > break; > - case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: > - pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); > - break; > case TRANS_DDI_MODE_SELECT_DP_SST: > if (encoder->type == INTEL_OUTPUT_EDP) > pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); > @@ -3604,6 +3610,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, > pipe_config->infoframes.enable |= > intel_hdmi_infoframes_enabled(encoder, pipe_config); > break; > + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: > + if (!HAS_DP20(dev_priv)) { > + /* FDI */ > + pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); > + break; > + } > + fallthrough; /* 128b/132b */ > case TRANS_DDI_MODE_SELECT_DP_MST: > pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); > pipe_config->lane_count = > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote: > There's a new register pair for 128b/132b mode where you need to set the > pixel clock in Hz. > > v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper > > Bspec: 54128 > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d104441344c0..97af19fd9780 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > > clear_act_sent(encoder, pipe_config); > > + if (intel_dp_is_uhbr(pipe_config)) { > + const struct drm_display_mode *adjusted_mode = > + &pipe_config->hw.adjusted_mode; > + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); > + > + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), > + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); > + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), > + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); > + } > + > intel_ddi_enable_transcoder_func(encoder, pipe_config); > > intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote: > There's a new register pair for 128b/132b mode where you need to set the > pixel clock in Hz. > > v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper > > Bspec: 54128 > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d104441344c0..97af19fd9780 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > > clear_act_sent(encoder, pipe_config); > > + if (intel_dp_is_uhbr(pipe_config)) { > + const struct drm_display_mode *adjusted_mode = > + &pipe_config->hw.adjusted_mode; > + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); > + > + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), > + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); > + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), > + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); > + } > + > intel_ddi_enable_transcoder_func(encoder, pipe_config); > > intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, 09 Sep 2021, Jani Nikula <jani.nikula@intel.com> wrote: > v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks > and the already merged patches obviously dropped. > > Jani Nikula (13): > drm/dp: add DP 2.0 UHBR link rate and bw code conversions > drm/dp: use more of the extended receiver cap > drm/dp: add LTTPR DP 2.0 DPCD addresses > drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Maarten, Maxime, Thomas, can I get an ack to merge these four patches via drm-intel please, or would you prefer a topic branch instead? Thanks, Jani. > drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode > drm/i915/dp: add helper for checking for UHBR link rate > drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates > drm/i915/dp: select 128b/132b channel encoding for UHBR rates > drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 > drm/i915/dp: add HAS_DP20 macro > drm/i915/dg2: use 128b/132b transcoder DDI mode > drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b > drm/i915/dg2: update link training for 128b/132b > > drivers/gpu/drm/drm_dp_helper.c | 42 +++++++- > drivers/gpu/drm/i915/display/intel_ddi.c | 61 +++++++++--- > drivers/gpu/drm/i915/display/intel_dp.c | 6 ++ > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > .../drm/i915/display/intel_dp_link_training.c | 99 +++++++++++++------ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_reg.h | 2 +- > include/drm/drm_dp_helper.h | 6 ++ > 9 files changed, 180 insertions(+), 49 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
On Thu, 09 Sep 2021, Jani Nikula <jani.nikula@intel.com> wrote: > v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks > and the already merged patches obviously dropped. > > Jani Nikula (13): > drm/dp: add DP 2.0 UHBR link rate and bw code conversions > drm/dp: use more of the extended receiver cap > drm/dp: add LTTPR DP 2.0 DPCD addresses > drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Maarten, Maxime, Thomas, can I get an ack to merge these four patches via drm-intel please, or would you prefer a topic branch instead? Thanks, Jani. > drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode > drm/i915/dp: add helper for checking for UHBR link rate > drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates > drm/i915/dp: select 128b/132b channel encoding for UHBR rates > drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 > drm/i915/dp: add HAS_DP20 macro > drm/i915/dg2: use 128b/132b transcoder DDI mode > drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b > drm/i915/dg2: update link training for 128b/132b > > drivers/gpu/drm/drm_dp_helper.c | 42 +++++++- > drivers/gpu/drm/i915/display/intel_ddi.c | 61 +++++++++--- > drivers/gpu/drm/i915/display/intel_dp.c | 6 ++ > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > .../drm/i915/display/intel_dp_link_training.c | 99 +++++++++++++------ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++ > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_reg.h | 2 +- > include/drm/drm_dp_helper.h | 6 ++ > 9 files changed, 180 insertions(+), 49 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
On Thu, Sep 09, 2021 at 03:51:57PM +0300, Jani Nikula wrote: > Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register > conflicts with FDI. Since we have to deal with both meanings in the same > code, for different platforms, clarify the macro name so we don't > forget. > > Bspec: 50493 > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 23ef291f7b30..2361f48537b5 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -489,7 +489,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, > if (crtc_state->hdmi_high_tmds_clock_ratio) > temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; > } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { > - temp |= TRANS_DDI_MODE_SELECT_FDI; > + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; > temp |= (crtc_state->fdi_lanes - 1) << 1; > } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { > temp |= TRANS_DDI_MODE_SELECT_DP_MST; > @@ -679,7 +679,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) > ret = false; > break; > > - case TRANS_DDI_MODE_SELECT_FDI: > + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: > ret = type == DRM_MODE_CONNECTOR_VGA; > break; > > @@ -3558,7 +3558,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, > pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); > pipe_config->lane_count = 4; > break; > - case TRANS_DDI_MODE_SELECT_FDI: > + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: > pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); > break; > case TRANS_DDI_MODE_SELECT_DP_SST: > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c2853cc005ee..03a94389c514 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -10202,7 +10202,7 @@ enum skl_power_gate { > #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) > #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) > #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) > -#define TRANS_DDI_MODE_SELECT_FDI (4 << 24) > +#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) > #define TRANS_DDI_BPC_MASK (7 << 20) > #define TRANS_DDI_BPC_8 (0 << 20) > #define TRANS_DDI_BPC_10 (1 << 20) > -- > 2.30.2 -- Ville Syrjälä Intel
On Thu, Sep 09, 2021 at 03:51:57PM +0300, Jani Nikula wrote: > Unfortunately, the DP 2.0 128b/132b DDI mode selection in the register > conflicts with FDI. Since we have to deal with both meanings in the same > code, for different platforms, clarify the macro name so we don't > forget. > > Bspec: 50493 > Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 23ef291f7b30..2361f48537b5 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -489,7 +489,7 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, > if (crtc_state->hdmi_high_tmds_clock_ratio) > temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; > } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { > - temp |= TRANS_DDI_MODE_SELECT_FDI; > + temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; > temp |= (crtc_state->fdi_lanes - 1) << 1; > } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { > temp |= TRANS_DDI_MODE_SELECT_DP_MST; > @@ -679,7 +679,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) > ret = false; > break; > > - case TRANS_DDI_MODE_SELECT_FDI: > + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: > ret = type == DRM_MODE_CONNECTOR_VGA; > break; > > @@ -3558,7 +3558,7 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, > pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); > pipe_config->lane_count = 4; > break; > - case TRANS_DDI_MODE_SELECT_FDI: > + case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: > pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); > break; > case TRANS_DDI_MODE_SELECT_DP_SST: > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c2853cc005ee..03a94389c514 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -10202,7 +10202,7 @@ enum skl_power_gate { > #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) > #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) > #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) > -#define TRANS_DDI_MODE_SELECT_FDI (4 << 24) > +#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) > #define TRANS_DDI_BPC_MASK (7 << 20) > #define TRANS_DDI_BPC_8 (0 << 20) > #define TRANS_DDI_BPC_10 (1 << 20) > -- > 2.30.2 -- Ville Syrjälä Intel
[-- Attachment #1: Type: text/plain, Size: 727 bytes --] On Fri, Sep 17, 2021 at 03:54:23PM +0300, Jani Nikula wrote: > On Thu, 09 Sep 2021, Jani Nikula <jani.nikula@intel.com> wrote: > > v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks > > and the already merged patches obviously dropped. > > > > Jani Nikula (13): > > drm/dp: add DP 2.0 UHBR link rate and bw code conversions > > drm/dp: use more of the extended receiver cap > > drm/dp: add LTTPR DP 2.0 DPCD addresses > > drm/dp: add helper for extracting adjust 128b/132b TX FFE preset > > Maarten, Maxime, Thomas, can I get an ack to merge these four patches > via drm-intel please, or would you prefer a topic branch instead? Yes, you can merge them through drm-intel Maxime [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #1: Type: text/plain, Size: 727 bytes --] On Fri, Sep 17, 2021 at 03:54:23PM +0300, Jani Nikula wrote: > On Thu, 09 Sep 2021, Jani Nikula <jani.nikula@intel.com> wrote: > > v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks > > and the already merged patches obviously dropped. > > > > Jani Nikula (13): > > drm/dp: add DP 2.0 UHBR link rate and bw code conversions > > drm/dp: use more of the extended receiver cap > > drm/dp: add LTTPR DP 2.0 DPCD addresses > > drm/dp: add helper for extracting adjust 128b/132b TX FFE preset > > Maarten, Maxime, Thomas, can I get an ack to merge these four patches > via drm-intel please, or would you prefer a topic branch instead? Yes, you can merge them through drm-intel Maxime [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --]
On Fri, 17 Sep 2021, Maxime Ripard <maxime@cerno.tech> wrote:
> On Fri, Sep 17, 2021 at 03:54:23PM +0300, Jani Nikula wrote:
>> On Thu, 09 Sep 2021, Jani Nikula <jani.nikula@intel.com> wrote:
>> > v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks
>> > and the already merged patches obviously dropped.
>> >
>> > Jani Nikula (13):
>> > drm/dp: add DP 2.0 UHBR link rate and bw code conversions
>> > drm/dp: use more of the extended receiver cap
>> > drm/dp: add LTTPR DP 2.0 DPCD addresses
>> > drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
>>
>> Maarten, Maxime, Thomas, can I get an ack to merge these four patches
>> via drm-intel please, or would you prefer a topic branch instead?
>
> Yes, you can merge them through drm-intel
Thanks, I've done that.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
On Fri, 17 Sep 2021, Maxime Ripard <maxime@cerno.tech> wrote:
> On Fri, Sep 17, 2021 at 03:54:23PM +0300, Jani Nikula wrote:
>> On Thu, 09 Sep 2021, Jani Nikula <jani.nikula@intel.com> wrote:
>> > v3 of https://patchwork.freedesktop.org/series/93800/ with minor tweaks
>> > and the already merged patches obviously dropped.
>> >
>> > Jani Nikula (13):
>> > drm/dp: add DP 2.0 UHBR link rate and bw code conversions
>> > drm/dp: use more of the extended receiver cap
>> > drm/dp: add LTTPR DP 2.0 DPCD addresses
>> > drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
>>
>> Maarten, Maxime, Thomas, can I get an ack to merge these four patches
>> via drm-intel please, or would you prefer a topic branch instead?
>
> Yes, you can merge them through drm-intel
Thanks, I've done that.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
On Fri, 17 Sep 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote: >> There's a new register pair for 128b/132b mode where you need to set the >> pixel clock in Hz. >> >> v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper >> >> Bspec: 54128 >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Thanks for the reviews, pushed up to and including this one. BR, Jani. > >> --- >> drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> index d104441344c0..97af19fd9780 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, >> >> clear_act_sent(encoder, pipe_config); >> >> + if (intel_dp_is_uhbr(pipe_config)) { >> + const struct drm_display_mode *adjusted_mode = >> + &pipe_config->hw.adjusted_mode; >> + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); >> + >> + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), >> + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); >> + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), >> + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); >> + } >> + >> intel_ddi_enable_transcoder_func(encoder, pipe_config); >> >> intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, >> -- >> 2.30.2 -- Jani Nikula, Intel Open Source Graphics Center
On Fri, 17 Sep 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote: >> There's a new register pair for 128b/132b mode where you need to set the >> pixel clock in Hz. >> >> v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper >> >> Bspec: 54128 >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Thanks for the reviews, pushed up to and including this one. BR, Jani. > >> --- >> drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> index d104441344c0..97af19fd9780 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, >> >> clear_act_sent(encoder, pipe_config); >> >> + if (intel_dp_is_uhbr(pipe_config)) { >> + const struct drm_display_mode *adjusted_mode = >> + &pipe_config->hw.adjusted_mode; >> + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); >> + >> + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), >> + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); >> + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), >> + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); >> + } >> + >> intel_ddi_enable_transcoder_func(encoder, pipe_config); >> >> intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, >> -- >> 2.30.2 -- Jani Nikula, Intel Open Source Graphics Center
On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote: > DP 2.0 brings some new DPCD addresses for PHY repeaters. > > Cc: dri-devel@lists.freedesktop.org > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > include/drm/drm_dp_helper.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 1d5b3dbb6e56..f3a61341011d 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1319,6 +1319,10 @@ struct drm_panel; > #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ > #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ > #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ > +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ > +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) > +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ > +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ > > enum drm_dp_phy { > DP_PHY_DPRX, > -- > 2.30.2 > > This patch causes a build failure in -next when combined with the AMD tree: In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ ^ ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 ^ 1 error generated. Perhaps something like this should be applied during the merge of the second tree or maybe this patch should be in a branch that could be shared between the Intel and AMD trees so that this diff could be applied to the AMD tree directly? Not sure what the standard procedure for this is. Cheers, Nathan diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 234dfbea926a..279863b5c650 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw = - lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES - + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; #endif diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index a5e798b5da79..8caf9af5ffa2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -878,8 +878,6 @@ struct psr_caps { # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) # define DP_DSC_DECODER_COUNT_SHIFT 5 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* TODO - Use DRM header to replace above once available */
[-- Attachment #1: Type: text/plain, Size: 3964 bytes --] Hi Nathan, On Tue, 21 Sep 2021 15:58:23 -0700 Nathan Chancellor <nathan@kernel.org> wrote: > > On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote: > > DP 2.0 brings some new DPCD addresses for PHY repeaters. > > > > Cc: dri-devel@lists.freedesktop.org > > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > --- > > include/drm/drm_dp_helper.h | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > > index 1d5b3dbb6e56..f3a61341011d 100644 > > --- a/include/drm/drm_dp_helper.h > > +++ b/include/drm/drm_dp_helper.h > > @@ -1319,6 +1319,10 @@ struct drm_panel; > > #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ > > #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ > > #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ > > +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ > > +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) > > +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ > > +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ > > > > enum drm_dp_phy { > > DP_PHY_DPRX, > > -- > > 2.30.2 > > > > > > This patch causes a build failure in -next when combined with the AMD > tree: > > In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: > In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: > In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: > ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] > #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ > ^ > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here > #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 > ^ > 1 error generated. > > Perhaps something like this should be applied during the merge of the > second tree or maybe this patch should be in a branch that could be > shared between the Intel and AMD trees so that this diff could be > applied to the AMD tree directly? Not sure what the standard procedure > for this is. > > Cheers, > Nathan > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > index 234dfbea926a..279863b5c650 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; > > link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw = > - lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES - > + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; > #endif > > diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h > index a5e798b5da79..8caf9af5ffa2 100644 > --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h > +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h > @@ -878,8 +878,6 @@ struct psr_caps { > # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) > # define DP_DSC_DECODER_COUNT_SHIFT 5 > #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 > -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 > -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 > #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 > #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) > /* TODO - Use DRM header to replace above once available */ Thanks for the heads up. I have applied the above as a merge fix patch until something else happens. -- Cheers, Stephen Rothwell [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 488 bytes --]
On Tue, 21 Sep 2021, Nathan Chancellor <nathan@kernel.org> wrote: > On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote: >> DP 2.0 brings some new DPCD addresses for PHY repeaters. >> >> Cc: dri-devel@lists.freedesktop.org >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> include/drm/drm_dp_helper.h | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >> index 1d5b3dbb6e56..f3a61341011d 100644 >> --- a/include/drm/drm_dp_helper.h >> +++ b/include/drm/drm_dp_helper.h >> @@ -1319,6 +1319,10 @@ struct drm_panel; >> #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ >> #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ >> #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ >> +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ >> +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) >> +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ >> +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ >> >> enum drm_dp_phy { >> DP_PHY_DPRX, >> -- >> 2.30.2 >> >> > > This patch causes a build failure in -next when combined with the AMD > tree: > > In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: > In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: > In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: > ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] > #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ > ^ > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here > #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 > ^ > 1 error generated. > > Perhaps something like this should be applied during the merge of the > second tree or maybe this patch should be in a branch that could be > shared between the Intel and AMD trees so that this diff could be > applied to the AMD tree directly? Not sure what the standard procedure > for this is. What's in the drm-intel-next branch is changing DRM DP helpers in include/drm/drm_dp_helper.h with acks from a drm-misc maintainer. That's where this stuff is supposed to land, not in a driver specific file, and especially not if added with just a DP_ prefix. BR, Jani. > > Cheers, > Nathan > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > index 234dfbea926a..279863b5c650 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c > @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; > > link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw = > - lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES - > + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES - > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; > #endif > > diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h > index a5e798b5da79..8caf9af5ffa2 100644 > --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h > +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h > @@ -878,8 +878,6 @@ struct psr_caps { > # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) > # define DP_DSC_DECODER_COUNT_SHIFT 5 > #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 > -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 > -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 > #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 > #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) > /* TODO - Use DRM header to replace above once available */ -- Jani Nikula, Intel Open Source Graphics Center
== Series Details == Series: drm/i915/dp: dp 2.0 enabling prep work (rev4) URL : https://patchwork.freedesktop.org/series/93800/ State : failure == Summary == Applying: drm/dp: add DP 2.0 UHBR link rate and bw code conversions Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_dp_helper.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/drm_dp_helper.c No changes -- Patch already applied. Applying: drm/dp: use more of the extended receiver cap Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_dp_helper.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/drm_dp_helper.c No changes -- Patch already applied. Applying: drm/dp: add LTTPR DP 2.0 DPCD addresses error: sha1 information is lacking or useless (drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0003 drm/dp: add LTTPR DP 2.0 DPCD addresses When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
+ Harry, Leo
Can you guys get someone to clean this up?
Alex
On Wed, Sep 22, 2021 at 7:10 AM Jani Nikula <jani.nikula@intel.com> wrote:
>
> On Tue, 21 Sep 2021, Nathan Chancellor <nathan@kernel.org> wrote:
> > On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
> >> DP 2.0 brings some new DPCD addresses for PHY repeaters.
> >>
> >> Cc: dri-devel@lists.freedesktop.org
> >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> include/drm/drm_dp_helper.h | 4 ++++
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> >> index 1d5b3dbb6e56..f3a61341011d 100644
> >> --- a/include/drm/drm_dp_helper.h
> >> +++ b/include/drm/drm_dp_helper.h
> >> @@ -1319,6 +1319,10 @@ struct drm_panel;
> >> #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
> >> #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
> >> #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
> >> +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> >> +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
> >> +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
> >> +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
> >>
> >> enum drm_dp_phy {
> >> DP_PHY_DPRX,
> >> --
> >> 2.30.2
> >>
> >>
> >
> > This patch causes a build failure in -next when combined with the AMD
> > tree:
> >
> > In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
> > In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
> > In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
> > ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
> > #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> > ^
> > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
> > #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> > ^
> > 1 error generated.
> >
> > Perhaps something like this should be applied during the merge of the
> > second tree or maybe this patch should be in a branch that could be
> > shared between the Intel and AMD trees so that this diff could be
> > applied to the AMD tree directly? Not sure what the standard procedure
> > for this is.
>
> What's in the drm-intel-next branch is changing DRM DP helpers in
> include/drm/drm_dp_helper.h with acks from a drm-misc maintainer. That's
> where this stuff is supposed to land, not in a driver specific file, and
> especially not if added with just a DP_ prefix.
>
>
> BR,
> Jani.
>
> >
> > Cheers,
> > Nathan
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > index 234dfbea926a..279863b5c650 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
> > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> >
> > link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
> > - lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
> > + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
> > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> > #endif
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> > index a5e798b5da79..8caf9af5ffa2 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> > +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> > @@ -878,8 +878,6 @@ struct psr_caps {
> > # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> > # define DP_DSC_DECODER_COUNT_SHIFT 5
> > #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
> > -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> > -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
> > #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
> > #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
> > /* TODO - Use DRM header to replace above once available */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
+ Harry, Leo
Can you guys get someone to clean this up?
Alex
On Wed, Sep 22, 2021 at 7:10 AM Jani Nikula <jani.nikula@intel.com> wrote:
>
> On Tue, 21 Sep 2021, Nathan Chancellor <nathan@kernel.org> wrote:
> > On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
> >> DP 2.0 brings some new DPCD addresses for PHY repeaters.
> >>
> >> Cc: dri-devel@lists.freedesktop.org
> >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> include/drm/drm_dp_helper.h | 4 ++++
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> >> index 1d5b3dbb6e56..f3a61341011d 100644
> >> --- a/include/drm/drm_dp_helper.h
> >> +++ b/include/drm/drm_dp_helper.h
> >> @@ -1319,6 +1319,10 @@ struct drm_panel;
> >> #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
> >> #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
> >> #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
> >> +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> >> +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
> >> +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
> >> +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
> >>
> >> enum drm_dp_phy {
> >> DP_PHY_DPRX,
> >> --
> >> 2.30.2
> >>
> >>
> >
> > This patch causes a build failure in -next when combined with the AMD
> > tree:
> >
> > In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
> > In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
> > In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
> > ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
> > #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> > ^
> > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
> > #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> > ^
> > 1 error generated.
> >
> > Perhaps something like this should be applied during the merge of the
> > second tree or maybe this patch should be in a branch that could be
> > shared between the Intel and AMD trees so that this diff could be
> > applied to the AMD tree directly? Not sure what the standard procedure
> > for this is.
>
> What's in the drm-intel-next branch is changing DRM DP helpers in
> include/drm/drm_dp_helper.h with acks from a drm-misc maintainer. That's
> where this stuff is supposed to land, not in a driver specific file, and
> especially not if added with just a DP_ prefix.
>
>
> BR,
> Jani.
>
> >
> > Cheers,
> > Nathan
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > index 234dfbea926a..279863b5c650 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
> > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> >
> > link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
> > - lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
> > + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
> > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> > #endif
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> > index a5e798b5da79..8caf9af5ffa2 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> > +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> > @@ -878,8 +878,6 @@ struct psr_caps {
> > # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> > # define DP_DSC_DECODER_COUNT_SHIFT 5
> > #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
> > -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> > -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
> > #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
> > #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
> > /* TODO - Use DRM header to replace above once available */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
[Why] For some reason we're defining DP 2.0 definitions inside our driver. Now that patches to introduce relevant definitions are slated to be merged into drm-next this is causing conflicts. In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] ^ ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here ^ 1 error generated. [How] Guard all display driver defines with #ifndef for now. Once we pull in the new definitions into amd-staging-drm-next we will follow up and drop definitions from our driver and provide follow-up header updates for any addition DP 2.0 definitions required by our driver. Signed-off-by: Harry Wentland <harry.wentland@amd.com> --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 53 ++++++++++++++++++-- 1 file changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index a5e798b5da79..74b8de616dcd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -860,28 +860,71 @@ struct psr_caps { }; #if defined(CONFIG_DRM_AMD_DC_DCN) +#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP #define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006 +#endif +#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 +#endif +#ifndef DP_FEC_CAPABILITY_1 #define DP_FEC_CAPABILITY_1 0x091 +#endif +#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 +#endif +#ifndef DP_DSC_CONFIGURATION #define DP_DSC_CONFIGURATION 0x161 +#endif +#ifndef DP_PHY_SQUARE_PATTERN #define DP_PHY_SQUARE_PATTERN 0x249 +#endif +#ifndef DP_128b_132b_SUPPORTED_LINK_RATES #define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215 +#endif +#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 +#endif +#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT #define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260 +#endif +#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 -# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) -# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) -# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 -# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) -# define DP_DSC_DECODER_COUNT_SHIFT 5 +#endif +#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK +#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 +#endif +#ifndef DP_DSC_DECODER_COUNT_MASK +#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +#endif +#ifndef DP_DSC_DECODER_COUNT_SHIFT +#define DP_DSC_DECODER_COUNT_SHIFT 5 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 +#endif +#ifndef DP_PHY_REPEATER_128b_132b_RATES #define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 +#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 +#endif +#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) +#endif /* TODO - Use DRM header to replace above once available */ union dp_main_line_channel_coding_cap { -- 2.33.0
[Why] For some reason we're defining DP 2.0 definitions inside our driver. Now that patches to introduce relevant definitions are slated to be merged into drm-next this is causing conflicts. In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] ^ ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here ^ 1 error generated. [How] Guard all display driver defines with #ifndef for now. Once we pull in the new definitions into amd-staging-drm-next we will follow up and drop definitions from our driver and provide follow-up header updates for any addition DP 2.0 definitions required by our driver. Signed-off-by: Harry Wentland <harry.wentland@amd.com> --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 53 ++++++++++++++++++-- 1 file changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index a5e798b5da79..74b8de616dcd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -860,28 +860,71 @@ struct psr_caps { }; #if defined(CONFIG_DRM_AMD_DC_DCN) +#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP #define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006 +#endif +#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 +#endif +#ifndef DP_FEC_CAPABILITY_1 #define DP_FEC_CAPABILITY_1 0x091 +#endif +#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 +#endif +#ifndef DP_DSC_CONFIGURATION #define DP_DSC_CONFIGURATION 0x161 +#endif +#ifndef DP_PHY_SQUARE_PATTERN #define DP_PHY_SQUARE_PATTERN 0x249 +#endif +#ifndef DP_128b_132b_SUPPORTED_LINK_RATES #define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215 +#endif +#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 +#endif +#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT #define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260 +#endif +#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 -# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) -# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) -# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 -# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) -# define DP_DSC_DECODER_COUNT_SHIFT 5 +#endif +#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK +#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 +#endif +#ifndef DP_DSC_DECODER_COUNT_MASK +#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +#endif +#ifndef DP_DSC_DECODER_COUNT_SHIFT +#define DP_DSC_DECODER_COUNT_SHIFT 5 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 +#endif +#ifndef DP_PHY_REPEATER_128b_132b_RATES #define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 +#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 +#endif +#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) +#endif /* TODO - Use DRM header to replace above once available */ union dp_main_line_channel_coding_cap { -- 2.33.0
== Series Details == Series: drm/i915/dp: dp 2.0 enabling prep work (rev5) URL : https://patchwork.freedesktop.org/series/93800/ State : failure == Summary == Applying: drm/dp: add DP 2.0 UHBR link rate and bw code conversions Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_dp_helper.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/drm_dp_helper.c No changes -- Patch already applied. Applying: drm/dp: use more of the extended receiver cap Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_dp_helper.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/drm_dp_helper.c No changes -- Patch already applied. Applying: drm/amd/display: Only define DP 2.0 symbols if not already defined error: sha1 information is lacking or useless (drivers/gpu/drm/amd/display/dc/dc_dp_types.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0003 drm/amd/display: Only define DP 2.0 symbols if not already defined When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".