From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60629) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkChO-00041u-BC for qemu-devel@nongnu.org; Wed, 14 Sep 2016 12:06:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bkChJ-00044Z-LB for qemu-devel@nongnu.org; Wed, 14 Sep 2016 12:06:10 -0400 Received: from mail-wm0-f47.google.com ([74.125.82.47]:37387) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkChJ-00044U-ES for qemu-devel@nongnu.org; Wed, 14 Sep 2016 12:06:05 -0400 Received: by mail-wm0-f47.google.com with SMTP id k186so16358713wmd.0 for ; Wed, 14 Sep 2016 09:06:05 -0700 (PDT) References: <1472935202-3342-1-git-send-email-rth@twiddle.net> <1472935202-3342-29-git-send-email-rth@twiddle.net> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1472935202-3342-29-git-send-email-rth@twiddle.net> Date: Wed, 14 Sep 2016 17:05:03 +0100 Message-ID: <87mvjaii1c.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v3 28/34] target-arm: emulate SWP with atomic_xchg helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, "Emilio G. Cota" Richard Henderson writes: > From: "Emilio G. Cota" > > Signed-off-by: Emilio G. Cota > Message-Id: <1467054136-10430-25-git-send-email-cota@braap.org> > Signed-off-by: Richard Henderson > --- > target-arm/translate.c | 25 +++++++++++++------------ > 1 file changed, 13 insertions(+), 12 deletions(-) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 680635c..2b3c34f 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -8741,25 +8741,26 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) > } > tcg_temp_free_i32(addr); > } else { > + TCGv taddr; > + TCGMemOp opc = s->be_data; > + > /* SWP instruction */ > rm = (insn) & 0xf; > > - /* ??? This is not really atomic. However we know > - we never have multiple CPUs running in parallel, > - so it is good enough. */ > - addr = load_reg(s, rn); > - tmp = load_reg(s, rm); > - tmp2 = tcg_temp_new_i32(); > if (insn & (1 << 22)) { > - gen_aa32_ld8u(s, tmp2, addr, get_mem_index(s)); > - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); > + opc |= MO_UB; > } else { > - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); > - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); > + opc |= MO_UL | MO_ALIGN; > } > - tcg_temp_free_i32(tmp); > + > + addr = load_reg(s, rn); > + taddr = gen_aa32_addr(s, addr, opc); > tcg_temp_free_i32(addr); > - store_reg(s, rd, tmp2); > + > + tmp = load_reg(s, rm); > + tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, > + get_mem_index(s), opc); > + store_reg(s, rd, tmp); > } > } > } else { Reviewed-by: Alex Bennée -- Alex Bennée