From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7A9AC6FD1D for ; Tue, 21 Mar 2023 17:13:38 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 29B841FE; Tue, 21 Mar 2023 18:12:46 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 29B841FE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1679418816; bh=GZ2jUeTUCoLsgOPhL0fTGLaijRLvdapi4CTxCCln2DY=; h=From:To:Subject:In-Reply-To:References:Date:CC:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; b=vq68QUcFHKi6HzhFY3FOdo4G1P0potYjqJaTLobbDeA4Jk6TewF93sCh4ZfuDqcy1 8EoOtRFH9TW8VSXsZ2Rq6NTiscuFqK8H24U9siATmR7jjIftKimhKJAVY3dEIZ24Yh sMYrjR8bMpDnYwSJagHxl5IOF47eUul71pELuaIc= Received: from mailman-core.alsa-project.org (mailman-core.alsa-project.org [10.254.200.10]) by alsa1.perex.cz (Postfix) with ESMTP id 4BD50F8027B; Tue, 21 Mar 2023 18:12:24 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id EB18BF8027B; Tue, 21 Mar 2023 18:12:19 +0100 (CET) Received: from mail.mutex.one (mail.mutex.one [62.77.152.124]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 5CD73F8024E for ; Tue, 21 Mar 2023 18:12:14 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 5CD73F8024E Authentication-Results: alsa1.perex.cz; dkim=pass (1024-bit key, unprotected) header.d=mutex.one header.i=@mutex.one header.a=rsa-sha256 header.s=default header.b=lDwXhBhf Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.mutex.one (Postfix) with ESMTP id C75EA16C0007; Tue, 21 Mar 2023 19:12:13 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at mail.mutex.one Received: from mail.mutex.one ([127.0.0.1]) by localhost (mail.mutex.one [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BQI5JdkOs9dG; Tue, 21 Mar 2023 19:12:12 +0200 (EET) From: Marian Postevca DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mutex.one; s=default; t=1679418732; bh=GZ2jUeTUCoLsgOPhL0fTGLaijRLvdapi4CTxCCln2DY=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=lDwXhBhf0yBAEAq5F0/8uf8/P1ckYfa0vxFaifa6SoqP0X3uYbZ5Kn35wla/k42xJ ktVwSR/gmIMjs01JlZTGbFvD1y/ChlEBI9jkbgCp09aaeCbBAlhQMHVAWrtbYN0O7m jm9BAmHK5ddJpUc+qqyL28kET69Vwki2hWUddWc8= To: Mark Brown , zhuning@everest-semi.com, yangxiaohua@everest-semi.com Subject: Re: [PATCH 1/4] ASoC: es8316: Enable support for S32 LE format and MCLK div by 2 In-Reply-To: <6825a54e-f2c0-41c4-981c-fafcd10454fd@sirena.org.uk> References: <20230320203519.20137-1-posteuca@mutex.one> <20230320203519.20137-2-posteuca@mutex.one> <6825a54e-f2c0-41c4-981c-fafcd10454fd@sirena.org.uk> Date: Tue, 21 Mar 2023 19:09:43 +0200 Message-ID: <87o7omvxns.fsf@mutex.one> MIME-Version: 1.0 Content-Type: text/plain Message-ID-Hash: 2H6RCHCIIVS6CAJCD22XMFHET6KEHFHZ X-Message-ID-Hash: 2H6RCHCIIVS6CAJCD22XMFHET6KEHFHZ X-MailFrom: posteuca@mutex.one X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: Takashi Iwai , Liam Girdwood , linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Thanks for taking the time to review this series of patches. Mark Brown writes: > On Mon, Mar 20, 2023 at 10:35:16PM +0200, Marian Postevca wrote: > >> To properly support a line of Huawei laptops with AMD CPU and a >> ES8336 codec connected to the ACP3X module we need to enable >> the S32 LE format and the codec option to divide the MCLK by 2. > > The 32 bit support and MCLK division are two separate changes so should > be two separate patches. > Ok, no problem, I just thought that a separate commit for one line was overkill. >> - lrck_divider = es8316->sysclk / params_rate(params); >> + >> + mclk_div_option = device_property_read_bool(component->dev, >> + "everest,mclk-div-by-2"); >> + if (mclk_div_option) { > > This introduces a DT property but there's no documentation for it, but I > don't see why we'd want this in the bindings - the driver should be able > to tell from the input clock rate and required output/internal clocks if > it needs to divide MCLK. The problem here is that I have no knowledge what is the maximum MCLK that the codec accepts. According to the datasheet the maximum supported frequency of MCLK is 51.2 Mhz. But this doesn't seem to be the case in practice since a MCLK of 48Mhz causes noises in the sound output. The idea to divide the MCLK by 2 was proposed by a Everest Semiconductor engineer. So I don't know how to make this generic enough to be activated from the codec driver. I cced the Everest Semiconductor engineers, maybe they have a proposal on how to activate this. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35F83C74A5B for ; Tue, 21 Mar 2023 17:34:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229923AbjCUReL (ORCPT ); Tue, 21 Mar 2023 13:34:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230150AbjCUReF (ORCPT ); Tue, 21 Mar 2023 13:34:05 -0400 Received: from mail.mutex.one (mail.mutex.one [62.77.152.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8A2051CAA for ; Tue, 21 Mar 2023 10:33:45 -0700 (PDT) Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.mutex.one (Postfix) with ESMTP id C75EA16C0007; Tue, 21 Mar 2023 19:12:13 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at mail.mutex.one Received: from mail.mutex.one ([127.0.0.1]) by localhost (mail.mutex.one [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BQI5JdkOs9dG; Tue, 21 Mar 2023 19:12:12 +0200 (EET) From: Marian Postevca DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=mutex.one; s=default; t=1679418732; bh=GZ2jUeTUCoLsgOPhL0fTGLaijRLvdapi4CTxCCln2DY=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=lDwXhBhf0yBAEAq5F0/8uf8/P1ckYfa0vxFaifa6SoqP0X3uYbZ5Kn35wla/k42xJ ktVwSR/gmIMjs01JlZTGbFvD1y/ChlEBI9jkbgCp09aaeCbBAlhQMHVAWrtbYN0O7m jm9BAmHK5ddJpUc+qqyL28kET69Vwki2hWUddWc8= To: Mark Brown , zhuning@everest-semi.com, yangxiaohua@everest-semi.com Cc: Takashi Iwai , Liam Girdwood , Jaroslav Kysela , linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org Subject: Re: [PATCH 1/4] ASoC: es8316: Enable support for S32 LE format and MCLK div by 2 In-Reply-To: <6825a54e-f2c0-41c4-981c-fafcd10454fd@sirena.org.uk> References: <20230320203519.20137-1-posteuca@mutex.one> <20230320203519.20137-2-posteuca@mutex.one> <6825a54e-f2c0-41c4-981c-fafcd10454fd@sirena.org.uk> Date: Tue, 21 Mar 2023 19:09:43 +0200 Message-ID: <87o7omvxns.fsf@mutex.one> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks for taking the time to review this series of patches. Mark Brown writes: > On Mon, Mar 20, 2023 at 10:35:16PM +0200, Marian Postevca wrote: > >> To properly support a line of Huawei laptops with AMD CPU and a >> ES8336 codec connected to the ACP3X module we need to enable >> the S32 LE format and the codec option to divide the MCLK by 2. > > The 32 bit support and MCLK division are two separate changes so should > be two separate patches. > Ok, no problem, I just thought that a separate commit for one line was overkill. >> - lrck_divider = es8316->sysclk / params_rate(params); >> + >> + mclk_div_option = device_property_read_bool(component->dev, >> + "everest,mclk-div-by-2"); >> + if (mclk_div_option) { > > This introduces a DT property but there's no documentation for it, but I > don't see why we'd want this in the bindings - the driver should be able > to tell from the input clock rate and required output/internal clocks if > it needs to divide MCLK. The problem here is that I have no knowledge what is the maximum MCLK that the codec accepts. According to the datasheet the maximum supported frequency of MCLK is 51.2 Mhz. But this doesn't seem to be the case in practice since a MCLK of 48Mhz causes noises in the sound output. The idea to divide the MCLK by 2 was proposed by a Everest Semiconductor engineer. So I don't know how to make this generic enough to be activated from the codec driver. I cced the Everest Semiconductor engineers, maybe they have a proposal on how to activate this.