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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-xe] [PATCH v2] drm/xe: Add fake workaround to maintain backward compatible in MI_BATCH_BUFFER_START X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Mon, 30 Jan 2023, Jos=C3=A9 Roberto de Souza wrot= e: > i915 has the same fake workaround to return MI_BATCH_BUFFER_START > nested batch buffer behavior in DG2 and newer platforms to the same > behavior as older platforms. > > So here cleaning up TGL_NESTED_BB_EN in MI_MODE to disable third level > chained batch buffer level. > > v2: > - replace IP_VERSION_FOREVER by XE_RTP_END_VERSION_UNDEFINED > - move fake workaround to lrc_additional_programming table > > Bspec: 45974, 45718 > Cc: Lucas De Marchi > Cc: Matt Roper > Signed-off-by: Jos=C3=A9 Roberto de Souza > --- > drivers/gpu/drm/xe/xe_gt.c | 1 + > drivers/gpu/drm/xe/xe_wa.c | 28 ++++++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_wa.h | 1 + > 3 files changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c > index 84a73eeccd297..5d07e1e7bd506 100644 > --- a/drivers/gpu/drm/xe/xe_gt.c > +++ b/drivers/gpu/drm/xe/xe_gt.c > @@ -311,6 +311,7 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) >=20=20 > xe_reg_sr_init(&hwe->reg_lrc, "LRC", xe); > xe_wa_process_lrc(hwe); > + xe_wa_process_lrc_additional_programming(hwe); >=20=20 > default_lrc =3D drmm_kzalloc(&xe->drm, > xe_lrc_size(xe, hwe->class), > diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c > index 3325de3edf691..744b7d0982683 100644 > --- a/drivers/gpu/drm/xe/xe_wa.c > +++ b/drivers/gpu/drm/xe/xe_wa.c > @@ -288,6 +288,21 @@ static const struct xe_rtp_entry lrc_was[] =3D { > {} > }; >=20=20 > +static const struct xe_rtp_entry lrc_additional_programming[] =3D { > + { XE_RTP_NAME("FakeWaDisableNestedBBMode"), Please add newline after {, and indent with tabs not spaces. > + /* > + * This is a "fake" workaround defined by software to ensure we > + * maintain reliable, backward-compatible behavior for userspace with > + * regards to how nested MI_BATCH_BUFFER_START commands are handled. > + */ > + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINE= D)), > + XE_RTP_CLR(RING_MI_MODE(0), > + TGL_NESTED_BB_EN, > + XE_RTP_FLAG(MASKED_REG, ENGINE_BASE)) > + }, > + {} > +}; > + > static const struct xe_rtp_entry register_whitelist[] =3D { > { XE_RTP_NAME("WaAllowPMDepthAndInvocationCountAccessFromUMD, 140855686= 5"), > XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)= ), > @@ -362,6 +377,19 @@ void xe_wa_process_lrc(struct xe_hw_engine *hwe) > xe_rtp_process(lrc_was, &hwe->reg_lrc, hwe->gt, hwe); > } >=20=20 > +/** > + * xe_wa_process_lrc_additional_programming - process additional LRC pro= gramming > + * table > + * @hwe: engine instance to process workarounds for > + * > + * Process additional context programming table for this platform, savin= g in > + * @hwe all the registers changes that need to be applied on context res= tore. > + */ > +void xe_wa_process_lrc_additional_programming(struct xe_hw_engine *hwe) > +{ > + xe_rtp_process(lrc_additional_programming, &hwe->reg_lrc, hwe->gt, hwe); > +} > + > /** > * xe_reg_whitelist_process_engine - process table of registers to white= list > * @hwe: engine instance to process whitelist for > diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h > index 1a0659690a320..872f3e4ddc73c 100644 > --- a/drivers/gpu/drm/xe/xe_wa.h > +++ b/drivers/gpu/drm/xe/xe_wa.h > @@ -12,6 +12,7 @@ struct xe_hw_engine; > void xe_wa_process_gt(struct xe_gt *gt); > void xe_wa_process_engine(struct xe_hw_engine *hwe); > void xe_wa_process_lrc(struct xe_hw_engine *hwe); > +void xe_wa_process_lrc_additional_programming(struct xe_hw_engine *hwe); >=20=20 > void xe_reg_whitelist_process_engine(struct xe_hw_engine *hwe); > void xe_reg_whitelist_apply(struct xe_hw_engine *hwe); --=20 Jani Nikula, Intel Open Source Graphics Center