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References: <20180425012300.14698-1-richard.henderson@linaro.org>
	<20180425012300.14698-8-richard.henderson@linaro.org>
From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
In-reply-to: <20180425012300.14698-8-richard.henderson@linaro.org>
Date: Tue, 01 May 2018 11:57:21 +0100
Message-ID: <87o9hzabji.fsf@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH 7/9] target/arm: Implement FCVT (scalar,
 fixed-point) for fp16
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To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org


Richard Henderson <richard.henderson@linaro.org> writes:

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>

> ---
>  target/arm/translate-a64.c | 17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 4f6317aa0f..794ede7222 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -5372,8 +5372,7 @@ static void disas_fp_fixed_conv(DisasContext *s, ui=
nt32_t insn)
>      bool sf =3D extract32(insn, 31, 1);
>      bool itof;
>
> -    if (sbit || (type > 1)
> -        || (!sf && scale < 32)) {
> +    if (sbit || (!sf && scale < 32)) {
>          unallocated_encoding(s);
>          return;
>      }
> @@ -5392,6 +5391,20 @@ static void disas_fp_fixed_conv(DisasContext *s, u=
int32_t insn)
>          return;
>      }
>
> +    switch (type) {
> +    case 0: /* float32 */
> +    case 1: /* float64 */
> +        break;
> +    case 3: /* float16 */
> +        if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
> +            break;
> +        }
> +        /* fallthru */
> +    default:
> +        unallocated_encoding(s);
> +        return;
> +    }
> +
>      if (!fp_access_check(s)) {
>          return;
>      }


--
Alex Benn=C3=A9e