From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45293) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1biMT5-0003Dp-VU for qemu-devel@nongnu.org; Fri, 09 Sep 2016 10:07:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1biMT0-0003vD-Tt for qemu-devel@nongnu.org; Fri, 09 Sep 2016 10:07:46 -0400 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]:35932) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1biMT0-0003uw-JM for qemu-devel@nongnu.org; Fri, 09 Sep 2016 10:07:42 -0400 Received: by mail-wm0-x22c.google.com with SMTP id b187so33563752wme.1 for ; Fri, 09 Sep 2016 07:07:42 -0700 (PDT) References: <1473417926-14263-1-git-send-email-nikunj@linux.vnet.ibm.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1473417926-14263-1-git-send-email-nikunj@linux.vnet.ibm.com> Date: Fri, 09 Sep 2016 15:07:40 +0100 Message-ID: <87oa3xxj2r.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH RFC v1 1/3] target-ppc: add TLB_NEED_LOCAL_FLUSH flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, benh@kernel.crashing.org, qemu-devel@nongnu.org, rth@twiddle.net Nikunj A Dadhania writes: I think we need a little more detail here. In fact when you post the next version of the series could you please include a cover letter to cover what the series is trying to achieve? > Signed-off-by: Nikunj A Dadhania > --- > target-ppc/cpu.h | 1 + > target-ppc/helper_regs.h | 2 +- > target-ppc/mmu-hash64.c | 4 ++-- > target-ppc/mmu_helper.c | 6 +++--- > 4 files changed, 7 insertions(+), 6 deletions(-) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 1e808c8..71111dc 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1009,6 +1009,7 @@ struct CPUPPCState { > bool tlb_dirty; /* Set to non-zero when modifying TLB */ > bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ > uint32_t tlb_need_flush; /* Delayed flush needed */ > +#define TLB_NEED_LOCAL_FLUSH 0x1 > #endif > > /* Other registers */ > diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h > index 3d279f1..4457a30 100644 > --- a/target-ppc/helper_regs.h > +++ b/target-ppc/helper_regs.h > @@ -157,7 +157,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, > static inline void check_tlb_flush(CPUPPCState *env) > { > CPUState *cs = CPU(ppc_env_get_cpu(env)); > - if (env->tlb_need_flush) { > + if ((env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) == TLB_NEED_LOCAL_FLUSH) { > env->tlb_need_flush = 0; > tlb_flush(cs, 1); > } > diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c > index 8118143..4c7ceef 100644 > --- a/target-ppc/mmu-hash64.c > +++ b/target-ppc/mmu-hash64.c > @@ -110,7 +110,7 @@ void helper_slbia(CPUPPCState *env) > * and we still don't have a tlb_flush_mask(env, n, mask) > * in QEMU, we just invalidate all TLBs > */ > - env->tlb_need_flush = 1; > + env->tlb_need_flush = TLB_NEED_LOCAL_FLUSH; I'm not sure what we gain here versus just using a straight bool for the flag. > } > } > } > @@ -132,7 +132,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr) > * and we still don't have a tlb_flush_mask(env, n, mask) > * in QEMU, we just invalidate all TLBs > */ > - env->tlb_need_flush = 1; > + env->tlb_need_flush = TLB_NEED_LOCAL_FLUSH; > } > } > > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index 696bb03..2498888 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -1965,7 +1965,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) > * we just mark the TLB to be flushed later (context synchronizing > * event or sync instruction on 32-bit). > */ > - env->tlb_need_flush = 1; > + env->tlb_need_flush = TLB_NEED_LOCAL_FLUSH; > break; > #if defined(TARGET_PPC64) > case POWERPC_MMU_64B: > @@ -1979,7 +1979,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) > * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, > * we just invalidate all TLBs > */ > - env->tlb_need_flush = 1; > + env->tlb_need_flush = TLB_NEED_LOCAL_FLUSH; > break; > #endif /* defined(TARGET_PPC64) */ > default: > @@ -2065,7 +2065,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) > } > } > #else > - env->tlb_need_flush = 1; > + env->tlb_need_flush = TLB_NEED_LOCAL_FLUSH; > #endif > } > } -- Alex Bennée