From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FD28C433EF for ; Fri, 28 Jan 2022 09:55:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347754AbiA1JzK (ORCPT ); Fri, 28 Jan 2022 04:55:10 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:59064 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232772AbiA1JzK (ORCPT ); Fri, 28 Jan 2022 04:55:10 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A4816B82355; Fri, 28 Jan 2022 09:55:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6D8A9C340EC; Fri, 28 Jan 2022 09:55:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643363707; bh=PtovFDT5iy2790+UdRGj4DUCZebF41LPL3rsZMT9Ew4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=dLQDgDC1f2X/hdh7969/9C+t8FWI7bt0qzm6uGiQg55Mn4cwIgbkVq+GIA+Zox2FN nLEvxa8Ym4PpudbOC5cR+le6ephiO82C/3KMk6laJIS7w1RHK8BMjxi0YJE1+im2M+ 5lapoRXu/i3uJyojGbOolk6m2TjvoQeLL7mEf3vj6MEZh7+PxAOgHW3V3BPNwbaR0M 0ErTedaGGgTsNMktz97yQ5O+rN8QO1Qk9DlGW7MjikGYH8rgfKRIxdNPYBjNR2UgbJ Wjv7k77Dv3rE9bl/eMJ1yic7zbhV03I2raMqfbhagcOep+tyIPSdNgfK7c1Iv+A2DQ wQYklX4PgXwGw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nDNyD-003lxY-EM; Fri, 28 Jan 2022 09:55:05 +0000 Date: Fri, 28 Jan 2022 09:55:04 +0000 Message-ID: <87pmoc5gnb.wl-maz@kernel.org> From: Marc Zyngier To: Bjorn Helgaas Cc: daire.mcnamara@microchip.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh@kernel.org, linux-pci@vger.kernel.org, robh+dt@kernel.org, devicetree@vger.kernel.org, david.abdurachmanov@gmail.com, cyril.jean@microchip.com Subject: Re: [PATCH v21 3/4] PCI: microchip: Add host driver for Microchip PCIe controller In-Reply-To: <20220127202000.GA126335@bhelgaas> References: <20210125162934.5335-4-daire.mcnamara@microchip.com> <20220127202000.GA126335@bhelgaas> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: helgaas@kernel.org, daire.mcnamara@microchip.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh@kernel.org, linux-pci@vger.kernel.org, robh+dt@kernel.org, devicetree@vger.kernel.org, david.abdurachmanov@gmail.com, cyril.jean@microchip.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 27 Jan 2022 20:20:00 +0000, Bjorn Helgaas wrote: > > [+cc Marc] > > On Mon, Jan 25, 2021 at 04:29:33PM +0000, daire.mcnamara@microchip.com wrote: > > From: Daire McNamara > > > > Add support for the Microchip PolarFire PCIe controller when > > configured in host (Root Complex) mode. > > > +static void mc_handle_msi(struct irq_desc *desc) > > +{ > > + struct mc_port *port = irq_desc_get_handler_data(desc); > > + struct device *dev = port->dev; > > + struct mc_msi *msi = &port->msi; > > + void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; > > + unsigned long status; > > + u32 bit; > > + u32 virq; > > + > > + status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); > > + if (status & PM_MSI_INT_MSI_MASK) { > > + status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); > > + for_each_set_bit(bit, &status, msi->num_vectors) { > > + virq = irq_find_mapping(msi->dev_domain, bit); > > + if (virq) > > + generic_handle_irq(virq); Wrong construct. Please use generic_handle_domain_irq(). > > + else > > + dev_err_ratelimited(dev, "bad MSI IRQ %d\n", bit); > > + } > > + } > > +} > > + > > +static void mc_msi_bottom_irq_ack(struct irq_data *data) > > +{ > > + struct mc_port *port = irq_data_get_irq_chip_data(data); > > + void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; > > + u32 bitpos = data->hwirq; > > + unsigned long status; > > + > > + writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); > > + status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); > > + if (!status) > > + writel_relaxed(BIT(PM_MSI_INT_MSI_SHIFT), bridge_base_addr + ISTATUS_LOCAL); > > This looks like it might be racy. What happens if we read 0 from > ISTATUS_MSI, but a new MSI is latched before we write ISTATUS_LOCAL? I agree, this looks really odd. The irq_ack callback is per interrupt, while this seems to deal with some global state. This cannot be right. M. -- Without deviation from the norm, progress is not possible.